Ruchir Puri

Haoxing Ren, Ruchir Puri, Lakshmi N. Reddy, Smita Krishnaswamy, Cindy Washburn, Joel Earl, Joachim Keinert: Intuitive ECO synthesis for high performance circuits. DATE 2013: 1002-1007

Hua Xiang, Minsik Cho, Haoxing Ren, Matthew M. Ziegler, Ruchir Puri: Network flow based datapath bit slicing. ISPD 2013: 139-146

Ruchir Puri: Opportunities and challenges for high performance microprocessor designs and design automation. ISPD 2013: 179

James D. Warnock, Yuen H. Chan, Hubert Harrer, David L. Rude, Ruchir Puri, Sean M. Carey, Gerard Salem, Guenter Mayer, Yiu-Hing Chan, Mark D. Mayo, Adam Jatkowski, Gerald Strevig, Leon J. Sigal, Ayan Datta, Anne Gattiker, Aditya Bansal, Doug Malone, Thomas Strach, Huajun Wen, Pak-kin Mak, Chung-Lung Shum, Donald W. Plass, Charles F. Webb: 5.5GHz system z microprocessor and multi-chip module. ISSCC 2013: 46-47

Ruchir Puri: Keynote talk: Opportunities and challenges for high performance microprocessor designs and design automation. VLSI Design 2013

Joshua Friedrich, Ruchir Puri, Uwe Brandt, Markus Buehler, Jack DiLullo, Jeremy Hopkins, Mozammel Hossain, Michael A. Kazda, Joachim Keinert, Zahi M. Kurzum, Douglass Lamb, Alice Lee, Frank Musante, Jens Noack, Peter J. Osler, Stephen Posluszny, Haifeng Qian, Shyam Ramji, Vasant B. Rao, Lakshmi N. Reddy, Haoxing Ren, Thomas E. Rosser, Benjamin R. Russell, Cliff C. N. Sze, Gustavo E. Téllez: Design methodology for the IBM POWER7 microprocessor. IBM Journal of Research and Development 55(3): 9 (2011)

Jeff Burns, Gary Carpenter, Eren Kursun, Ruchir Puri, James D. Warnock, Michael Scheuermann: Design, CAD and technology challenges for future processors: 3D perspectives. DAC 2011: 212

Ruchir Puri, William H. Joyner, Raj Jammy, Ahmed Jerraya, Jan M. Rabaey, Walden C. Rhines, Leon Stok: EDA challenges and options: investing for the future. DAC 2010: 1-2

Minsik Cho, Haoxing Ren, Hua Xiang, Ruchir Puri: History-based VLSI legalization using network flow. DAC 2010: 286-291

Minsik Cho, David Z. Pan, Ruchir Puri: Novel binary linear programming for high performance clock mesh synthesis. ICCAD 2010: 438-443

Hua Xiang, Haoxing Ren, Louise Trevillyan, Lakshmi N. Reddy, Ruchir Puri, Minsik Cho: Logical and physical restructuring of fan-in trees. ISPD 2010: 67-74

Ruchir Puri, David S. Kung: The Dawn of 22nm Era: Design and CAD Challenges. VLSI Design 2010: 429-433

David S. Kung, Ruchir Puri: CAD challenges for 3D ICs. ASP-DAC 2009: 421-422

Ching Zhou, Bruce M. Fleischer, Michael Gschwind, Ruchir Puri: 64-bit prefix adders: Power-efficient topologies and design solutions. CICC 2009: 179-182

Jason Cong, N. S. Nagaraj, Ruchir Puri, William H. Joyner, Jeff Burns, Moshe Gavrielov, Riko Radojcic, Peter Rickert, Hans Stork: Moore's Law: another casualty of the financial meltdown? DAC 2009: 202-203

Ruchir Puri, Eshel Haritan, Stan Krolikoski, Jason Cong, Tim Kogel, Bradley D. McCredie, John Shen, Andrés Takach: From milliwatts to megawatts: system level power challenge. DAC 2009: 750-751

Smita Krishnaswamy, Haoxing Ren, Nilesh Modi, Ruchir Puri: DeltaSyn: An efficient logic difference optimizer for ECO synthesis. ICCAD 2009: 789-796

Ruchir Puri: Will 22nm be our catch 22!: design and cad challenges. ISPD 2009: 59-60

Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong: Is Your Layout-Density Verification Exact? - A Fast Exact Deep Submicrometer Density Calculation Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 621-632 (2008)

Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong: Fast Dummy-Fill Density Analysis With Coupling Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 27(4): 633-642 (2008)

Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: Track Routing and Optimization for Yield. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 872-882 (2008)

Ruchir Puri, Devadas Varma, Darvin Edwards, Alan J. Weger, Paul D. Franzon, Andrew Yang, Stephen V. Kosonocky: Keeping hot chips cool: are IC thermal problems hot air? DAC 2008: 634-635

Ruchir Puri, William H. Joyner, Shekhar Borkar, Ty Garibay, Jonathan Lotz, Robert K. Montoye: Custom is from Venus and synthesis from Mars. DAC 2008: 992

Minsik Cho, Hua Xiang, Ruchir Puri, David Z. Pan: TROY: Track Router with Yield-driven Wire Planning. DAC 2007: 55-58

Srikanth Venkataraman, Ruchir Puri, Steve Griffith, Ankush Oberai, Robert Madge, Greg Yeric, Walter Ng, Yervant Zorian: Making Manufacturing Work For You. DAC 2007: 107-108

Kerry Bernstein, Paul Andry, Jerome Cann, Philip G. Emma, David Greenberg, Wilfried Haensch, Mike Ignatowski, Steven J. Koester, John Magerlein, Ruchir Puri, Albert M. Young: Interconnects in the Third Dimension: Design Challenges for 3D ICs. DAC 2007: 562-567

Hua Xiang, Liang Deng, Ruchir Puri, Kai-Yuan Chao, Martin D. F. Wong: Dummy fill density analysis with coupling constraints. ISPD 2007: 3-10

Hua Xiang, Kai-Yuan Chao, Ruchir Puri, Martin D. F. Wong: Is your layout density verification exact?: a fast exact algorithm for density calculation. ISPD 2007: 19-26

Ashish Kumar Singh, Murari Mani, Ruchir Puri, Michael Orshansky: Gain-based technology mapping for minimum runtime leakage under input vector uncertainty. DAC 2006: 522-527

David J. Frank, Ruchir Puri, Dorel Toma: Design and CAD challenges in 45nm CMOS and beyond. ICCAD 2006: 329-333

Minsik Cho, David Z. Pan, Hua Xiang, Ruchir Puri: Wire density driven global routing for CMP variation and timing. ICCAD 2006: 487-492

Ruchir Puri, Tanay Karnik, Rajiv V. Joshi: Technology Impacts on Sub-90nm CMOS Circuit Design and Design Methodologies. VLSI Design 2006: 5-7

Ruchir Puri, Leon Stok, Subhrajit Bhattacharya: Keeping hot chips cool. DAC 2005: 285-288

Ruchir Puri, David S. Kung, Leon Stok: Minimizing power with flexible voltage islands. ISCAS (1) 2005: 21-24

Anirudh Devgan, Ruchir Puri, Sachin Sapatnaker, Tanay Karnik, Rajiv V. Joshi: Design of sub-90nm Circuits and Design Methodologies. ISQED 2005: 3-4

Louise Trevillyan, David S. Kung, Ruchir Puri, Lakshmi N. Reddy, Michael A. Kazda: An Integrated Environment for Technology Closure of Deep-Submicron IC Designs. IEEE Design & Test of Computers 21(1): 14-22 (2004)

Ruchir Puri, Leon Stok, John M. Cohn, David S. Kung, David Z. Pan, Dennis Sylvester, Ashish Srivastava, Sarvesh H. Kulkarni: Pushing ASIC performance in a power envelope. DAC 2003: 788-793

Kerry Bernstein, Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri: Design and CAD Challenges in sub-90nm CMOS Technologies. ICCAD 2003: 129-137

Ching-Te Chuang, Rajiv V. Joshi, Ruchir Puri, Keunwoo Kim: Design Considerations of Scaled Sub-0.1 ?m PD/SOI CMOS Circuits. ISQED 2003: 153-158

Ruchir Puri, David S. Kung, Anthony D. Drumm: Fast and accurate wire delay estimation for physical synthesis of large ASICs. ACM Great Lakes Symposium on VLSI 2002: 30-36

Frederik Beeftink, Prabhakar Kudva, David S. Kung, Ruchir Puri, Leon Stok: Combinatorial cell design for CMOS libraries. Integration 29(1): 67-93 (2000)

Ruchir Puri, Ching-Te Chuang: SOI Digital Circuits: Design Issues. VLSI Design 2000: 474-479

Ching-Te Chuang, Ruchir Puri: SOI Digital CMOS VLSI - a Design Perspective. DAC 1999: 709-714

David S. Kung, Ruchir Puri: Optimal P/N width ratio selection for standard cell libraries. ICCAD 1999: 178-184

Ruchir Puri, Ching-Te Chuang: Hysteresis effect in floating-body partially-depleted SOI CMOS domino circuits. ISLPED 1999: 223-228

Ruchir Puri: Design issues in mixed static-domino circuit implementations. ICCD 1998: 270-275

Ruchir Puri, Jun Gu: A BDD SAT Solver for Satisfiability Testing: An Industrial Case Study. Ann. Math. Artif. Intell. 17(3-4): 315-337 (1996)

Ruchir Puri, Andrew Bjorksten, Thomas E. Rosser: Logic optimization by output phase assignment in dynamic logic synthesis. ICCAD 1996: 2-7

Jun Gu, Ruchir Puri: Asynchronous circuit synthesis with Boolean satisfiability. IEEE Trans. on CAD of Integrated Circuits and Systems 14(8): 961-973 (1995)

Ruchir Puri, Jun Gu: A Modular Partitioning Approach for Asynchronous Circuit Synthesis. DAC 1994: 63-69

Ruchir Puri, Jun Gu: Area Efficient Synthesis of Asynchronous Interface Circuits. ICCD 1994: 212-216

Ruchir Puri, Jun Gu: An efficient algorithm to search for minimal closed covers in sequential machines. IEEE Trans. on CAD of Integrated Circuits and Systems 12(6): 737-745 (1993)

Ruchir Puri, Jun Gu: Microword length minimization in microprogrammed controller synthesis. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1449-1457 (1993)

Ruchir Puri, Jun Gu: Signal Transition Graph Constraints for Speed-independent Ciruit Synthesis. ISCAS 1993: 1686-1689

Ruchir Puri, Jun Gu: An Efficient algorithm for Microword Length Minimization. DAC 1992: 651-656