| 2012 | ||
|---|---|---|
| c6 | Steven J. E. Wilton, Bradley R. Quinton, Eddie Hung: Rapid RTL-based signal ranking for FPGA prototyping. FPT 2012: 1-7 | |
| 2009 | ||
| j3 | Bradley R. Quinton, Steven J. E. Wilton: Programmable Logic Core Enhancements for High-Speed On-Chip Interfaces. IEEE Trans. VLSI Syst. 17(9): 1334-1339 (2009) | |
| 2008 | ||
| j2 | Steven J. E. Wilton, Chun Hok Ho, Bradley R. Quinton, Philip Heng Wai Leong, Wayne Luk: A Synthesizable Datapath-Oriented Embedded FPGA Fabric for Silicon Debug Applications. TRETS 1(1) (2008) | |
| j1 | Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton: Practical Asynchronous Interconnect Network Design. IEEE Trans. VLSI Syst. 16(5): 579-588 (2008) | |
| 2007 | ||
| c5 | Steven J. E. Wilton, Chun Hok Ho, Philip Heng Wai Leong, Wayne Luk, Bradley R. Quinton: A synthesizable datapath-oriented embedded FPGA fabric. FPGA 2007: 33-41 | |
| c4 | Bradley R. Quinton, Steven J. E. Wilton: Embedded Programmable Logic Core Enhancements for System Bus Interfaces. FPL 2007: 202-209 | |
| 2005 | ||
| c3 | Bradley R. Quinton, Steven J. E. Wilton: Post-Silicon Debug Using Programmable Logic Cores. FPT 2005: 241-248 | |
| c2 | Bradley R. Quinton, Mark R. Greenstreet, Steven J. E. Wilton: Asynchronous IC Interconnect Network Design and Implementation Using a Standard ASIC Flow. ICCD 2005: 267-274 | |
| c1 | Bradley R. Quinton, Steven J. E. Wilton: Concentrator access networks for programmable logic cores on SoCs. ISCAS (1) 2005: 45-48 | |
| 1 | Mark R. Greenstreet | |
| 2 | Chun Hok Ho | |
| 3 | Eddie Hung | |
| 4 | Philip Heng Wai Leong | |
| 5 | Wayne Luk | |
| 6 | Steven J. E. Wilton |
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