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 | 2013 | |
|---|---|---|
| c22 |      | Moinuddin K. Qureshi: Embedded tutorial - Emerging memory technologies: What it means for computer system designers. VLSI Design 2013 |
| 2012 | ||
| c21 | | Jaewoong Sim, Jaekyu Lee, Moinuddin K. Qureshi, Hyesoon Kim: FLEXclusion: Balancing cache capacity and on-chip bandwidth via Flexible Exclusion. ISCA 2012: 321-332 |
| c20 | | Moinuddin K. Qureshi, Michele Franceschini, Ashish Jagmohan, Luis Lastras: PreSET: Improving performance of phase change memories by exploiting asymmetry in write times. ISCA 2012: 380-391 |
| c19 | | Moinuddin K. Qureshi, Gabe H. Loh: Fundamental Latency Trade-off in Architecting DRAM Caches: Outperforming Impractical SRAM-Tags with a Simple and Practical Design. MICRO 2012: 235-246 |
| 2011 | ||
| b1 | | Moinuddin K. Qureshi, Sudhanva Gurumurthi, Bipin Rajendran: Phase Change Memory: From Devices to Systems. Synthesis Lectures on Computer Architecture, Morgan & Claypool Publishers 2011 |
| c18 | | Moinuddin K. Qureshi, André Seznec, Luis Lastras, Michele Franceschini: Practical and secure PCM systems by online detection of malicious write streams. HPCA 2011: 478-489 |
| c17 | | Moinuddin K. Qureshi: Pay-As-You-Go: low-overhead hard-error correction for phase change memories. MICRO 2011: 318-328 |
| 2010 | ||
| j2 | | M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt: Accelerating Critical Section Execution with Asymmetric Multicore Architectures. IEEE Micro 30(1): 60-70 (2010) |
| c16 | | M. Aater Suleman, Moinuddin K. Qureshi, Khubaib, Yale N. Patt: Feedback-directed pipeline parallelism. PACT 2010: 147-156 |
| c15 | | Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño: Improving read performance of Phase Change Memories via Write Cancellation and Write Pausing. HPCA 2010: 1-11 |
| c14 | | Moinuddin K. Qureshi, Michele Franceschini, Luis Alfonso Lastras-Montaño, John P. Karidis: Morphable memory system: a robust architecture for exploiting multi-level phase change memories. ISCA 2010: 153-162 |
| 2009 | ||
| c13 | | M. Aater Suleman, Onur Mutlu, Moinuddin K. Qureshi, Yale N. Patt: Accelerating critical section execution with asymmetric multi-core architectures. ASPLOS 2009: 253-264 |
| c12 | | Moinuddin K. Qureshi: Adaptive Spill-Receive for robust high-performance caching in CMPs. HPCA 2009: 45-54 |
| c11 | | Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers: Scalable high performance main memory system using phase-change memory technology. ISCA 2009: 24-33 |
| c10 | | Moinuddin K. Qureshi, John P. Karidis, Michele Franceschini, Vijayalakshmi Srinivasan, Luis Lastras, Bülent Abali: Enhancing lifetime and security of PCM-based main memory with start-gap wear leveling. MICRO 2009: 14-23 |
| c9 | | Jason Zebchuk, Vijayalakshmi Srinivasan, Moinuddin K. Qureshi, Andreas Moshovos: A tagless coherence directory. MICRO 2009: 423-434 |
| 2008 | ||
| j1 | | Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer: Set-Dueling-Controlled Adaptive Insertion for High-Performance Caching. IEEE Micro 28(1): 91-98 (2008) |
| c8 | | Aamer Jaleel, William Hasenplaugh, Moinuddin K. Qureshi, Julien Sebot, Simon C. Steely Jr., Joel S. Emer: Adaptive insertion policies for managing shared caches. PACT 2008: 208-219 |
| c7 | | M. Aater Suleman, Moinuddin K. Qureshi, Yale N. Patt: Feedback-driven threading: power-efficient and high-performance execution of multi-threaded workloads on CMPs. ASPLOS 2008: 277-286 |
| 2007 | ||
| c6 | | Moinuddin K. Qureshi, M. Aater Suleman, Yale N. Patt: Line Distillation: Increasing Cache Capacity by Filtering Unused Words in Cache Lines. HPCA 2007: 250-259 |
| c5 | | Moinuddin K. Qureshi, Aamer Jaleel, Yale N. Patt, Simon C. Steely Jr., Joel S. Emer: Adaptive insertion policies for high performance caching. ISCA 2007: 381-391 |
| 2006 | ||
| c4 | | Moinuddin K. Qureshi, Daniel N. Lynch, Onur Mutlu, Yale N. Patt: A Case for MLP-Aware Cache Replacement. ISCA 2006: 167-178 |
| c3 | | Moinuddin K. Qureshi, Yale N. Patt: Utility-Based Cache Partitioning: A Low-Overhead, High-Performance, Runtime Mechanism to Partition Shared Caches. MICRO 2006: 423-432 |
| 2005 | ||
| c2 | | Moinuddin K. Qureshi, Onur Mutlu, Yale N. Patt: Microarchitecture-Based Introspection: A Technique for Transient-Fault Tolerance in Microprocessors. DSN 2005: 434-443 |
| c1 | | Moinuddin K. Qureshi, David Thompson, Yale N. Patt: The V-Way Cache: Demand Based Associativity via Global Replacement. ISCA 2005: 544-555 |
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