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Steffen Rülke
2010 – today
- 2012
[c21]Thilo Vörtler, Steffen Rülke, Petra Hofstedt: Bounded model checking of Contiki applications. DDECS 2012: 258-261
2000 – 2009
- 2009
- [j1]Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Advanced verification by automatic property generation. IET Computers & Digital Techniques 3(4): 338-353 (2009)
- [c20]Frank Rogin, Rolf Drechsler, Steffen Rülke: Automatic debugging of System-on-a-Chip designs. SoCC 2009: 333-336
- 2008
- [c19]Frank Rogin, Thomas Klotz, Görschwin Fey, Rolf Drechsler, Steffen Rülke: Automatic Generation of Complex Properties for Hardware Designs. DATE 2008: 545-548
- [c18]Maik Boden, Thomas Fiebig, Markus Reiband, Peter Reichel, Steffen Rülke: GePaRD - A High-Level Generation Flow for Partially Reconfigurable Designs. ISVLSI 2008: 298-303
- 2007
- [c17]Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt: A Run-Time Scheduling Framework for a Reconfigurable Hardware Emulator. DSD 2007: 147-150
- [c16]Frank Rogin, Christian Genz, Rolf Drechsler, Steffen Rülke: An Integrated SystemC Debugging Environment. FDL 2007: 140-145
- [c15]Maik Boden, Thomas Fiebig, Torsten Meibner, Steffen Rülke, Jürgen Becker: High-Level Synthesis of HW Tasks Targeting Run-Time Reconfigurable FPGAs. IPDPS 2007: 1-8
- [c14]Rene Beckert, Thomas Fuchs, Steffen Rülke, Wolfram Hardt: A Tailored Design Partitioning Method for Hardware Emulation. IEEE International Workshop on Rapid System Prototyping 2007: 99-105
- 2006
- [c13]Frank Rogin, Erhard Fehlauer, Steffen Rülke, Sebastian Ohnewald, Thomas Berndt: Non-Intrusive High-level SystemC Debugging. FDL 2006: 155-161
- [c12]Maik Boden, Steffen Rülke, Jürgen Becker: A high-level target-precise model for designing reconfigurable HW tasks. IPDPS 2006
- 2005
- [c11]Maik Boden, Alex Gleich, Steffen Rülke, Ulrich Nageldinger: A Low-Cost Realization of an Adaptable Protocol Processing Unit. IPDPS 2005
- 2004
- [c10]Maik Boden, Manfred Koegst, José Luis Tiburcio Badía, Steffen Rülke: Cost-Efficient Implementation of Adaptive Finite State Machines. DSD 2004: 144-151
- [c9]Hans-Jürgen Brand, Steffen Rülke, Martin Radetzki: IPQ: IP Qualification for Efficient System Design. ISQED 2004: 478-482
- [c8]Jörg Schneider, Vincent Kotzsch, Steffen Rülke: Demonstrator: Reuse Automation for Reconfigurable System-on-Chip Design within a DVB Environment. PARELEC 2004: 177-180
- 2002
- [c7]Maik Boden, Jörg Schneider, Klaus Feske, Steffen Rülke: Enhanced Reusability for SoC-Based HW/SW Co-Design. DSD 2002: 94-101
- [c6]Ronny Frevert, Steffen Rülke, Torsten Schäfer, Frank Dresig: Use of HDL Code Checkers to Support the IP Entrance Check - A Requirement Analysis. DSD 2002: 364-370
- [c5]Jörg Schneider, Maik Boden, Steffen Rülke: Eine wiederverwendungsgerechte Entwurfsmethodik für rekonfigurierbare SoC-Architekturen. MBMV 2002: 36-45
- 2001
- [c4]Manfred Koegst, Steffen Rülke, Günter Franke, Maria J. Avedillo: Two-Criterial Constraint-Driven FSM State Encoding for Low Power. DSD 2001: 94-101
1990 – 1999
- 1998
- [c3]Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske: Multi-Criterial State Assignment for Low Power FSM Design. EUROMICRO 1998: 10261-10268
- [c2]Manfred Koegst, Günter Franke, Klaus Feske, Steffen Rülke: Verringerung der Leistungsaufnahme in sequentiellen Schaltungen durch Vorlogik und zweistufige Zustandskodierung. MBMV 1998: 30-37
- 1997
- [c1]Manfred Koegst, Günter Franke, Steffen Rülke, Klaus Feske: Low Power Design of FSMs by State Assignment and Disabling Self-Loops. EUROMICRO 1997: 323-330
Coauthor Index
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last updated on 2012-12-02 20:58 CET by the dblp team