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Katarzyna Radecka
2010 – today
- 2013
[j8]Omid Sarbishei, Katarzyna Radecka: On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications. IEEE Trans. on CAD of Integrated Circuits and Systems 32(6): 831-844 (2013)- 2012
- [j7]Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic: Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 31(3): 343-355 (2012)
- [c29]Omid Sarbishei, Katarzyna Radecka: Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations. ASP-DAC 2012: 789-794
- [c28]Atena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic: MSE minimization and fault-tolerant data fusion for multi-sensor systems. ICCD 2012: 445-452
- [c27]Omid Sarbishei, Katarzyna Radecka: Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT). ISCAS 2012: 592-595
- [c26]Majid Janidarmian, Zeljko Zilic, Katarzyna Radecka: Issues in Multi-valued Multi-modal Sensor Fusion. ISMVL 2012: 238-243
- 2011
- [c25]Omid Sarbishei, Katarzyna Radecka: On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers. IEEE Symposium on Computer Arithmetic 2011: 62-69
- [c24]Yu Pang, Katarzyna Radecka, Zeljko Zilic: An efficient hybrid engine to perform range analysis and allocate integer bit-widths for arithmetic circuits. ASP-DAC 2011: 455-460
- [c23]Sayeeda Sultana, Katarzyna Radecka, Yu Pang: A study on relating redundancy removal in classical circuits to reversible mapping. ICCD 2011: 206-211
- [c22]Yu Pang, Shaoquan Wang, Zhilong He, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka: Positive Davio-based synthesis algorithm for reversible logic. ICCD 2011: 212-218
- [c21]Sayeeda Sultana, Katarzyna Radecka: Reversible implementation of square-root circuit. ICECS 2011: 141-144
- [c20]O. Sarbishei, Katarzyna Radecka: Analysis of Mean-Square-Error (MSE) for fixed-point FFT units. ISCAS 2011: 1732-1735
- [c19]Yu Pang, Katarzyna Radecka: An efficient algorithm of performing range analysis for fixed-point arithmetic circuits based on SAT checking. ISCAS 2011: 1736-1739
- [c18]Yu Pang, Jinzhao Lin, Sayeeda Sultana, Katarzyna Radecka: A novel method of synthesizing reversible logic. ISCAS 2011: 2857-2860
- [c17]Sayeeda Sultana, Katarzyna Radecka: Rev-Map: A Direct Gateway from Classical Irreversible Network to Reversible Network. ISMVL 2011: 147-152
- [c16]Zeljko Zilic, Katarzyna Radecka: Fault tolerant glucose sensor readout and recalibration. Wireless Health 2011: 35
- 2010
- [j6]Yu Pang, Katarzyna Radecka, Zeljko Zilic: Optimization of Imprecise Circuits Represented by Taylor Series and Real-Valued Polynomials. IEEE Trans. on CAD of Integrated Circuits and Systems 29(8): 1177-1190 (2010)
- [c15]O. Sarbishei, Yu Pang, Katarzyna Radecka: Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks. HLDVT 2010: 25-32
- [c14]O. Sarbishei, Katarzyna Radecka: Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits. ICCAD 2010: 739-745
- [c13]Yu Pang, Katarzyna Radecka, Zeljko Zilic: An efficient method to perform range analysis for DSP circuits. ICECS 2010: 855-858
2000 – 2009
- 2008
- [j5]Sayeeda Sultana, Shahriar Al-Imam, Katarzyna Radecka: Design for Testability of QCA Logic Under Stuck-at-value Fault Model. Multiple-Valued Logic and Soft Computing 14(1-2): 145-176 (2008)
- [c12]
- 2007
- [j4]Ali Khazamipour, Katarzyna Radecka: Adiabatic Implementation of Reversible Logic Circuits in CMOS Technology. Multiple-Valued Logic and Soft Computing 13(1-2): 191-216 (2007)
- [j3]Zeljko Zilic, Katarzyna Radecka: Scaling and Better Approximating Quantum Fourier Transform by Higher Radices. IEEE Trans. Computers 56(2): 202-207 (2007)
- [c11]Zeljko Zilic, Katarzyna Radecka, Ali Kazamiphur: Reversible circuit technology mapping from non-reversible specifications. DATE 2007: 558-563
- 2006
- [c10]Rong Zhang, Zeljko Zilic, Katarzyna Radecka: Energy Efficient Software-Based Self-Test for Wireless Sensor Network Nodes. VTS 2006: 186-191
- 2004
- [j2]Katarzyna Radecka, Zeljko Zilic: Design Verification by Test Vectors and Arithmetic Transform Universal Test Set. IEEE Trans. Computers 53(5): 628-640 (2004)
- [c9]Ahmed Usman Khalid, Zeljko Zilic, Katarzyna Radecka: FPGA Emulation of Quantum Circuits. ICCD 2004: 310-315
- [c8]Man Wah Chiang, Zeljko Zilic, Jean-Samuel Chenard, Katarzyna Radecka: Architectures of Increased Availability Wireless Sensor Network Nodes. ITC 2004: 1232-1241
- 2002
- [c7]Katarzyna Radecka, Zeljko Zilic: Specifying and verifying imprecise sequential datapaths by Arithmetic Transforms. ICCAD 2002: 128-131
- [c6]Zeljko Zilic, Katarzyna Radecka: The Role of Super-Fast Transforms in Speeding Up Quantum Computations. ISMVL 2002: 129-135
- [c5]Katarzyna Radecka, Zeljko Zilic: Identifying Redundant Wire Replacements for Synthesis and Verification. VLSI Design 2002: 517-523
- 2001
- [c4]Katarzyna Radecka, Zeljko Zilic: Arithmetic Transforms for Verifying Compositions of Sequential Datapaths. ICCD 2001: 348-353
- [c3]Zeljko Zilic, Katarzyna Radecka: : Identifying redundant gate replacements in verification by error modeling. ITC 2001: 803-812
- 2000
- [c2]Katarzyna Radecka, Zeljko Zilic: Using Arithmetic Transform for Verification of Datapath Circuits via Error Modeling. VTS 2000: 271-280
1990 – 1999
- 1999
- [c1]Zeljko Zilic, Katarzyna Radecka: On Feasible Multivariate Polynomial Interpolations over Arbitrary Fields. ISSAC 1999: 67-74
- 1997
- [j1]Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer: Arithmetic built-in self-test for DSP cores. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1358-1369 (1997)
Coauthor Index
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last updated on 2013-05-22 20:49 CEST by the dblp team