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Swarnalatha Radhakrishnan
2010 – today
- 2013
[c7]Tuo Li, Muhammad Shafique, Semeen Rehman, Swarnalatha Radhakrishnan, Roshan G. Ragel, Jude Angelo Ambrose, Jörg Henkel, Sri Parameswaran: CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors. DATE 2013: 707-712
[c6]Lawrance Zhang, Jude Angelo Ambrose, Jorgen Peddersen, Sri Parameswaran, Roshan G. Ragel, Swarnalatha Radhakrishnan, Kewal K. Saluja: DRMA: dynamically reconfigurable MPSoC architecture. ACM Great Lakes Symposium on VLSI 2013: 239-244
[c5]Roshan G. Ragel, Swarnalatha Radhakrishnan, Jude Angelo Ambrose, Sri Parameswaran: A Study on Instruction-set Selection Using Multi-application Based Application Specific Instruction-set Processors. VLSI Design 2013: 7-12- 2012
[c4]Mohammad Shihabul Haque, Roshan G. Ragel, Jude Angelo Ambrose, Swarnalatha Radhakrishnan, Sri Parameswaran: DIMSim: a rapid two-level cache simulation approach for deadline-based MPSoCs. CODES+ISSS 2012: 151-160
2000 – 2009
- 2009
[j1]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic: HMP-ASIPs: heterogeneous multi-pipeline application-specific instruction-set processors. IET Computers & Digital Techniques 3(1): 94-108 (2009)- 2006
[c3]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran, Aleksandar Ignjatovic: Application specific forwarding network and instruction encoding for multi-pipe ASIPs. CODES+ISSS 2006: 241-246
[c2]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran: Customization of application specific heterogeneous multi-pipeline processors. DATE 2006: 746-751- 2004
[c1]Swarnalatha Radhakrishnan, Hui Guo, Sri Parameswaran: Dual-pipeline heterogeneous ASIP design. CODES+ISSS 2004: 12-17
Coauthor Index
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last updated on 2013-06-18 22:45 CEST by the dblp team



