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Sreeranga P. Rajan
2010 – today
- 2012
[c19]Guodong Li, Peng Li, Geoffrey Sawaya, Ganesh Gopalakrishnan, Indradeep Ghosh, Sreeranga P. Rajan: GKLEE: concolic verification and test generation for GPUs. PPOPP 2012: 215-224- 2011
- [c18]Guodong Li, Indradeep Ghosh, Sreeranga P. Rajan: KLOVER: A Symbolic Execution and Automatic Test Generation Tool for C++ Programs. CAV 2011: 609-615
- [c17]Oksana Tkachuk, Sreeranga P. Rajan: Automated Driver Generation for Analysis of Web Applications. FASE 2011: 326-340
- [c16]Hideo Tanida, Masahiro Fujita, Mukul R. Prasad, Sreeranga P. Rajan: Client-tier Validation of Dynamic Web Applications. ICSOFT (2) 2011: 86-95
2000 – 2009
- 2009
- [c15]Sreeranga P. Rajan, Oksana Tkachuk, Mukul R. Prasad, Indradeep Ghosh, Nitin Goel, Tadahiro Uehara: WEAVE: WEb Applications Validation Environment. ICSE Companion 2009: 101-111
- 2008
- [c14]Xin Li, Daryl Shannon, Indradeep Ghosh, Mizuhito Ogawa, Sreeranga P. Rajan, Sarfraz Khurshid: Context-Sensitive Relevancy Analysis for Efficient Symbolic Execution. APLAS 2008: 36-52
- 2007
- [c13]Oksana Tkachuk, Sreeranga P. Rajan: Combining environment generation and slicing for modular software model checking. ASE 2007: 401-404
- 2006
- [j7]Graham Hughes, Sreeranga P. Rajan, Tom Sidle, Keith Swenson: Error Detection in Concurrent Java Programs. Electr. Notes Theor. Comput. Sci. 144(3): 45-58 (2006)
- [j6]David W. Currie, Xiushan Feng, Masahiro Fujita, Alan J. Hu, Mark Kwan, Sreeranga P. Rajan: Embedded Software Verification Using Symbolic Execution and Uninterpreted Functions. International Journal of Parallel Programming 34(1): 61-91 (2006)
- [c12]Oksana Tkachuk, Sreeranga P. Rajan: Application of automated environment generation to commercial software. ISSTA 2006: 203-214
- 2005
- [j5]
- 2004
- [c11]Praveen K. Murthy, Sreeranga P. Rajan, Koichiro Takayama: High level hardware validation using hierarchical message sequence charts. HLDVT 2004: 167-172
- 2002
- [j4]Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum: Program slicing for VHDL. STTT 4(1): 125-137 (2002)
- [c10]Subir K. Roy, S. Ramesh, Supratik Chakraborty, Tsuneo Nakata, Sreeranga P. Rajan: Functional Verification of System on Chips-Practices, Issues and Challenges (Tutorial Abstract). VLSI Design 2002: 11-13
- 2001
- [j3]Subramanian Rajagopalan, Sreeranga P. Rajan, Sharad Malik, Sandro Rigo, Guido Araujo, Koichiro Takayama: A retargetable VLIW compiler framework for DSPs withinstruction-level parallelism. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1319-1328 (2001)
- 2000
- [c9]David W. Currie, Alan J. Hu, Sreeranga P. Rajan: Automatic formal verification of DSP software. DAC 2000: 130-135
1990 – 1999
- 1999
- [c8]Vamsi Boppana, Sreeranga P. Rajan, Koichiro Takayama, Masahiro Fujita: Model Checking Based on Sequential ATPG. CAV 1999: 418-430
- [c7]Edmund M. Clarke, Masahiro Fujita, Sreeranga P. Rajan, Thomas W. Reps, Subash Shankar, Tim Teitelbaum: Program Slicing of Hardware Description Languages. CHARME 1999: 298-312
- [c6]Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik: Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. CODES 1999: 2-6
- 1998
- [j2]Sreeranga P. Rajan, Masahiro Fujita, K. Yuan, Mike Tien-Chien Lee: ATM switch design by high-level modeling, formal verification and high-level synthesi. ACM Trans. Design Autom. Electr. Syst. 3(4): 554-562 (1998)
- [c5]Masahiro Fujita, Sreeranga P. Rajan, Alan J. Hu: Two Real Formal Verification Experiences: ATM Switch Chip and Parallel Cache Protocol. FM-Trends 1998: 281-295
- [c4]Sreeranga P. Rajan, Masahiro Fujita: Integration of High-Level Modeling, Formal Verification, and High-Level Synthesis in ATM Switch Design. VLSI Design 1998: 552-557
- 1997
- [c3]Sreeranga P. Rajan, Masahiro Fujita: ATM Switch Design: Parametric High-Level Modeling and Formal Verification. AMAST 1997: 437-450
- 1996
- [j1]Peter F. A. Middelhoek, Sreeranga P. Rajan: From VHDL to efficient and first-time-right designs: a formal approach. ACM Trans. Design Autom. Electr. Syst. 1(2): 205-250 (1996)
- 1993
- [c2]Sreeranga P. Rajan, Jeffrey J. Joyce, Carl-Johan H. Seger: From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation. HUG 1993: 489-500
- 1992
- [c1]Sreeranga P. Rajan: Executing HOL Specifications: Towards an Evaluation Semantics for Classical Higher Order Logic. TPHOLs 1992: 527-536
Coauthor Index
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last updated on 2012-12-02 22:13 CET by the dblp team