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Janusz Rajski
2010 – today
- 2012
[j55]Jakub Janicki, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: EDT Bandwidth Management in SoC Designs. IEEE Trans. on CAD of Integrated Circuits and Systems 31(12): 1894-1907 (2012)- [c138]Xijiang Lin, Janusz Rajski: On Utilizing Test Cube Properties to Reduce Test Data Volume Further. Asian Test Symposium 2012: 83-88
- [c137]Jakub Janicki, Jerzy Tyszer, Grzegorz Mrugalski, Janusz Rajski: Bandwidth-aware test compression logic for SoC designs. European Test Symposium 2012: 1-6
- [c136]Dariusz Czysz, Janusz Rajski, Jerzy Tyszer: Low power test application with selective compaction in VLSI designs. ITC 2012: 1-10
- [c135]Friedrich Hapke, M. Reese, Jason Rivers, A. Over, V. Ravikumar, Wilfried Redemund, Andreas Glowatz, Jürgen Schlöffel, Janusz Rajski: Cell-aware Production test results from a 32-nm notebook processor. ITC 2012: 1-9
- [c134]Jedrzej Solecki, Jerzy Tyszer, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski: Low power programmable PRPG with enhanced fault coverage gradient. ITC 2012: 1-9
- [c133]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Benoit Nadeau-Dostie: Test generator with preselected toggling for low power built-in self-test. VTS 2012: 1-6
- 2011
- [j54]Nilanjan Mukherjee, Janusz Rajski, Grzegorz Mrugalski, Artur Pogiel, Jerzy Tyszer: Ring Generator: An Ultimate Linear Feedback Shift Register. IEEE Computer 44(6): 64-71 (2011)
- [j53]Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer: Fault Diagnosis with Orthogonal Compactors in Scan-Based Designs. J. Electronic Testing 27(5): 599-609 (2011)
- [j52]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: BIST-Based Fault Diagnosis for Read-Only Memories. IEEE Trans. on CAD of Integrated Circuits and Systems 30(7): 1072-1085 (2011)
- [j51]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, P. Szczerbicki, Jerzy Tyszer: Deterministic Clustering of Incompatible Test Cubes for Higher Power-Aware EDT Compression. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1225-1238 (2011)
- [c132]Michal Filipek, Yoshiaki Fukui, Hiroyuki Iwata, Grzegorz Mrugalski, Janusz Rajski, Masahiro Takakura, Jerzy Tyszer: Low Power Decompressor and PRPG with Constant Value Broadcast. Asian Test Symposium 2011: 84-89
- [c131]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Jakub Janicki: Low Test Data Volume Low Power At-Speed Delay Tests Using Clock-Gating. Asian Test Symposium 2011: 267-272
- [c130]Grzegorz Mrugalski, Artur Pogiel, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer, Pawel Urbanek: Fault Diagnosis in Memory BIST Environment with Non-march Tests. Asian Test Symposium 2011: 419-424
- [c129]Xijiang Lin, Elham K. Moghaddam, Nilanjan Mukherjee, Benoit Nadeau-Dostie, Janusz Rajski, Jerzy Tyszer: Power Aware Embedded Test. Asian Test Symposium 2011: 511-516
- [c128]Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer: Diagnosis of Failing Scan Cells through Orthogonal Response Compaction. European Test Symposium 2011: 1-6
- [c127]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Reduced ATE Interface for High Test Data Compression. European Test Symposium 2011: 99-104
- [c126]Friedrich Hapke, Jürgen Schlöffel, Wilfried Redemund, Andreas Glowatz, Janusz Rajski, M. Reese, J. Rearick, Jason Rivers: Cell-aware analysis for small-delay effects and production test results from different fault models. ITC 2011: 1-8
- [c125]Jakub Janicki, Jerzy Tyszer, Avijit Dutta, Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski: EDT channel bandwidth management in SoC designs with pattern-independent test access mechanism. ITC 2011: 1-9
- [c124]Janusz Rajski, Elham K. Moghaddam, Sudhakar M. Reddy: Low power compression utilizing clock-gating. ITC 2011: 1-8
- 2010
- [j50]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: On Compaction Utilizing Inter and Intra-Correlation of Unknown States. IEEE Trans. on CAD of Integrated Circuits and Systems 29(1): 117-126 (2010)
- [j49]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: High Volume Diagnosis in Memory BIST Based on Compressed Failure Data. IEEE Trans. on CAD of Integrated Circuits and Systems 29(3): 441-453 (2010)
- [c123]Xijiang Lin, Janusz Rajski: Adaptive Low Shift Power Test Pattern Generator for Logic BIST. Asian Test Symposium 2010: 355-360
- [c122]Brady Benware, Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer: Diagnosis of failing scan cells through orthogonal response compaction. European Test Symposium 2010: 221-226
- [c121]Mark Kassab, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jakub Janicki, Jerzy Tyszer: Dynamic channel allocation for higher EDT compression in SoC designs. ITC 2010: 265-274
- [c120]Dariusz Czysz, Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, P. Szczerbicki, Jerzy Tyszer: Low power compression of incompatible test cubes. ITC 2010: 704-713
- [c119]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Xijiang Lin, Nilanjan Mukherjee, Mark Kassab: Low capture power at-speed test in EDT environment. ITC 2010: 714-723
- [c118]Elham K. Moghaddam, Janusz Rajski, Sudhakar M. Reddy, Mark Kassab: At-speed scan test with low switching activity. VTS 2010: 177-182
2000 – 2009
- 2009
- [j48]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Timing-Aware Multiple-Delay-Fault Diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 28(2): 245-258 (2009)
- [j47]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Low-Power Scan Operation in Test Compression Environment. IEEE Trans. on CAD of Integrated Circuits and Systems 28(11): 1742-1755 (2009)
- [c117]Gang Chen, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz: N-distinguishing Tests for Enhanced Defect Diagnosis. Asian Test Symposium 2009: 183-186
- [c116]Santiago Remersaro, Janusz Rajski, Sudhakar M. Reddy, Irith Pomeranz: A scalable method for the generation of small test sets. DATE 2009: 1136-1141
- [c115]
- [c114]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer: Compression based on deterministic vector clustering of incompatible test cubes. ITC 2009: 1-10
- [c113]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: Fault diagnosis for embedded read-only memories. ITC 2009: 1-10
- [c112]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Defect Aware to Power Conscious Tests - The New DFT Landscape. VLSI Design 2009: 23-25
- [c111]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: High-Speed On-Chip Event Counters for Embedded Systems. VLSI Design 2009: 275-280
- [c110]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer: Highly X-Tolerant Selective Compaction of Test Responses. VTS 2009: 245-250
- 2008
- [j46]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab: X-Press: Two-Stage X-Tolerant Compactor With Programmable Selector. IEEE Trans. on CAD of Integrated Circuits and Systems 27(1): 147-159 (2008)
- [j45]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Improving the Resolution of Single-Delay-Fault Diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 27(5): 932-945 (2008)
- [j44]Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Low-Power Test Data Application in EDT Environment Through Decompressor Freeze. IEEE Trans. on CAD of Integrated Circuits and Systems 27(7): 1278-1290 (2008)
- [c109]Santiago Remersaro, Janusz Rajski, Thomas Rinderknecht, Sudhakar M. Reddy, Irith Pomeranz: ATPG Heuristics Dependant Observation Point Insertion for Enhanced Compaction and Data Volume Reduction. DFT 2008: 385-393
- [c108]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Timing-Aware Multiple-Delay-Fault Diagnosis. ISQED 2008: 246-253
- [c107]Dariusz Czysz, Mark Kassab, Xijiang Lin, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Low Power Scan Shift and Capture in the EDT Environment. ITC 2008: 1-10
- [c106]
- [c105]Nilanjan Mukherjee, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: High Throughput Diagnosis via Compression of Failure Data in Embedded Memory BIST. ITC 2008: 1-10
- 2007
- [j43]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Scan-Based Tests with Low Switching Activity. IEEE Design & Test of Computers 24(3): 268-275 (2007)
- [j42]Jerzy Tyszer, Janusz Rajski, Grzegorz Mrugalski, Nilanjan Mukherjee, Mark Kassab, Wu-Tung Cheng, Manish Sharma, Liyang Lai: X-Tolerant Compactor with On-Chip Registration and Signature-Based Diagnosis. IEEE Design & Test of Computers 24(5): 476-485 (2007)
- [j41]Grzegorz Mrugalski, Janusz Rajski, Chen Wang, Artur Pogiel, Jerzy Tyszer: Isolation of Failing Scan Cells through Convolutional Test Response Compaction. J. Electronic Testing 23(1): 35-45 (2007)
- [j40]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi: Enhancing delay fault coverage through low-power segmented scan. IET Computers & Digital Techniques 1(3): 220-229 (2007)
- [j39]Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: Fault Diagnosis With Convolutional Compactors. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1478-1494 (2007)
- [c104]Grzegorz Mrugalski, Janusz Rajski, Dariusz Czysz, Jerzy Tyszer: New Test Data Decompressor for Low Power Applications. DAC 2007: 539-544
- [c103]Dhiraj Goswami, Kun-Han Tsai, Mark Kassab, Janusz Rajski: Test Generation in the Presence of Timing Exceptions and Constraints. DAC 2007: 688-693
- [c102]
- [c101]Huaxing Tang, Manish Sharma, Janusz Rajski, Martin Keim, Brady Benware: Analyzing Volume Diagnosis Results with Statistical Learning for Yield Improvement. European Test Symposium 2007: 145-150
- [c100]Santiago Remersaro, Xijiang Lin, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Low Shift and Capture Power Scan Tests. VLSI Design 2007: 793-798
- [c99]Dariusz Czysz, Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Low Power Embedded Deterministic Test. VTS 2007: 75-83
- [c98]Chris Schuermyer, Jewel Pangilinan, Jay Jahangiri, Martin Keim, Janusz Rajski, Brady Benware: Silicon Evaluation of Static Alternative Fault Models. VTS 2007: 265-270
- [e1]Jill Sibert, Janusz Rajski (Eds.): 2007 IEEE International Test Conference, ITC 2007, Santa Clara, California, USA, October 21-26, 2007. IEEE 2007, ISBN 1-4244-1128-9
- 2006
- [j38]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: High Performance Dense Ring Generators. IEEE Trans. Computers 55(1): 83-87 (2006)
- [j37]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Analysis and methodology for multiple-fault diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 558-575 (2006)
- [c97]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: A test pattern ordering algorithm for diagnosis with truncated fail data. DAC 2006: 399-404
- [c96]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Test response compactor with programmable selector. DAC 2006: 1089-1094
- [c95]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Bashir M. Al-Hashimi: Enhancing Delay Fault Coverage through Low Power Segmented Scan. European Test Symposium 2006: 21-28
- [c94]Artur Pogiel, Janusz Rajski, Jerzy Tyszer: Convolutional Compactors with Variable Polynomials. European Test Symposium 2006: 117-122
- [c93]Vishal J. Mehta, Malgorzata Marek-Sadowska, Zhiyuan Wang, Kun-Han Tsai, Janusz Rajski: Delay Fault Diagnosis for Non-Robust Test. ISQED 2006: 463-472
- [c92]Yu Huang, Wu-Tung Cheng, Nagesh Tamarapalli, Janusz Rajski, Randy Klingenberg, Will Hsu, Yuan-Shih Chen: Diagnosis with Limited Failure Information. ITC 2006: 1-10
- [c91]Martin Keim, Nagesh Tamarapalli, Huaxing Tang, Manish Sharma, Janusz Rajski, Chris Schuermyer, Brady Benware: A Rapid Yield Learning Flow Based on Production Integrated Layout-Aware Diagnosis. ITC 2006: 1-10
- [c90]Vishal J. Mehta, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Timing Defect Diagnosis in Presence of Crosstalk for Nanometer Technology. ITC 2006: 1-10
- [c89]Janusz Rajski, Jerzy Tyszer, Grzegorz Mrugalski, Wu-Tung Cheng, Nilanjan Mukherjee, Mark Kassab: X-Press Compactor for 1000x Reduction of Test Data. ITC 2006: 1-10
- [c88]Santiago Remersaro, Xijiang Lin, Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: Preferred Fill: A Scalable Method to Reduce Capture Power for Scan Based Designs. ITC 2006: 1-10
- [c87]Gang Chen, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski: New Procedures to Identify Redundant Stuck-At Faults and Removal of Redundant Logic. VLSI Design 2006: 419-424
- [c86]Xijiang Lin, Janusz Rajski: The Impacts of Untestable Defects on Transition Fault Testing. VTS 2006: 2-7
- [c85]
- [c84]Zhuo Zhang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski: Scan Tests with Multiple Fault Activation Cycles for Delay Faults. VTS 2006: 343-348
- 2005
- [j36]Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy: Finite memory test response compactors for embedded test applications. IEEE Trans. on CAD of Integrated Circuits and Systems 24(4): 622-634 (2005)
- [j35]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Delay-fault diagnosis using timing information. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1315-1325 (2005)
- [c83]Xijiang Lin, Janusz Rajski: Propagation delay fault: a new fault model to test delay faults. ASP-DAC 2005: 178-183
- [c82]Janusz Rajski: Embedded Test Technology - Brief History, Current Status, and Future Directions. Asian Test Symposium 2005
- [c81]Huaxing Tang, Gang Chen, Sudhakar M. Reddy, Chen Wang, Janusz Rajski, Irith Pomeranz: Defect Aware Test Patterns. DATE 2005: 450-455
- [c80]
- [c79]Yu Huang, Wu-Tung Cheng, Janusz Rajski: Compressed pattern diagnosis for scan chain failures. ITC 2005: 8
- [c78]Grzegorz Mrugalski, Artur Pogiel, Janusz Rajski, Jerzy Tyszer: Diagnosis with convolutional compactors in presence of unknown states. ITC 2005: 10
- [c77]Huaxing Tang, Chen Wang, Janusz Rajski, Sudhakar M. Reddy, Jerzy Tyszer, Irith Pomeranz: On Efficient X-Handling Using a Selective Compaction Scheme to Achieve High Test Response Compaction Ratios. VLSI Design 2005: 59-64
- [c76]
- 2004
- [j34]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee: Embedded deterministic test. IEEE Trans. on CAD of Integrated Circuits and Systems 23(5): 776-792 (2004)
- [j33]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Ring generators - new devices for embedded test applications. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1306-1320 (2004)
- [c75]Wu-Tung Cheng, Kun-Han Tsai, Yu Huang, Nagesh Tamarapalli, Janusz Rajski: Compactor Independent Direct Diagnosis. Asian Test Symposium 2004: 204-209
- [c74]Janusz Rajski, Kan Thapar: Nanometer Design: What are the Requirements for Manufacturing Test? DATE 2004: 930-937
- [c73]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Diagnosis of Hold Time Defects. ICCD 2004: 192-199
- [c72]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Delay Fault Diagnosis Using Timing Information. ISQED 2004: 485-490
- [c71]Grzegorz Mrugalski, Chen Wang, Artur Pogiel, Jerzy Tyszer, Janusz Rajski: Fault Diagnosis in Designs with Convolutional Compactors. ITC 2004: 498-507
- [c70]Xinli Gu, Cyndee Wang, Abby Lee, Bill Eklow, Kun-Han Tsai, Jan Arild Tofte, Mark Kassab, Janusz Rajski: Realizing High Test Quality Goals with Smart Test Resource Usage. ITC 2004: 525-533
- [c69]Brady Benware, Cam Lu, John Van Slyke, Prabhu Krishnamurthy, Robert Madge, Martin Keim, Mark Kassab, Janusz Rajski: Affordable and Effective Screening of Delay Defects in ASICs using the Inline Resistance Fault Model. ITC 2004: 1285-1294
- [c68]Janusz Rajski, Nilanjan Mukherjee, Jerzy Tyszer, Thomas Rinderknecht: Embedded Test for Low Cost Manufacturing. VLSI Design 2004: 21-23
- [c67]Grzegorz Mrugalski, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Planar High Performance Ring Generators. VTS 2004: 193-198
- 2003
- [j32]Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski: 2D Test Sequence Generators. IEEE Design & Test of Computers 20(1): 51-59 (2003)
- [j31]Xijiang Lin, Ron Press, Janusz Rajski, Paul Reuter, Thomas Rinderknecht, Bruce Swanson, Nagesh Tamarapalli: High-Frequency, At-Speed Scan Testing. IEEE Design & Test of Computers 20(5): 17-25 (2003)
- [j30]Janusz Rajski, Mark Kassab, Nilanjan Mukherjee, Nagesh Tamarapalli, Jerzy Tyszer, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing. IEEE Design & Test of Computers 20(5): 58-66 (2003)
- [j29]Janusz Rajski, Jerzy Tyszer: Primitive Polynomials Over GF(2) of Degree up to 660 with Uniformly Distributed Coefficients. J. Electronic Testing 19(6): 645-657 (2003)
- [c66]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Janusz Rajski, Jerzy Tyszer: On Compacting Test Response Data Containing Unknown Values. ICCAD 2003: 855-862
- [c65]Zhiyuan Wang, Malgorzata Marek-Sadowska, Kun-Han Tsai, Janusz Rajski: Multiple Fault Diagnosis Using n-Detection Tests. ICCD 2003: 198-
- [c64]Janusz Rajski, Jerzy Tyszer: Test Data Compression and Compaction for Embedded Test of Nanometer Technology Designs. ICCD 2003: 331-
- [c63]
- [c62]Zhiyuan Wang, Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski: An Efficient and Effective Methodology on the Multiple Fault Diagnosis. ITC 2003: 329-338
- [c61]Janusz Rajski, Jerzy Tyszer, Chen Wang, Sudhakar M. Reddy: Convolutional Compaction of Test Responses. ITC 2003: 745-754
- [c60]Brady Benware, Chris Schuermyer, Sreenevasan Ranganathan, Robert Madge, Prabhu Krishnamurthy, Nagesh Tamarapalli, Kun-Han Tsai, Janusz Rajski: Impact of Multiple-Detect Test Patterns on Product Quality. ITC 2003: 1031-1040
- [c59]Frank Poehl, Matthias Beck, Ralf Arnold, Peter Muhmenthaler, Nagesh Tamarapalli, Mark Kassab, Nilanjan Mukherjee, Janusz Rajski: Industrial Experience with Adoption of EDT for Low-Cost Test without Concessions. ITC 2003: 1211-1220
- [c58]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: High Speed Ring Generators and Compactors of Test Data. VTS 2003: 57-62
- 2002
- [c57]Irith Pomeranz, Janusz Rajski, Sudhakar M. Reddy: Finding a Common Fault Response for Diagnosis during Silicon Debug. DATE 2002: 1116
- [c56]Chen Wang, Sudhakar M. Reddy, Irith Pomeranz, Xijiang Lin, Janusz Rajski: Conflict driven techniques for improving deterministic test pattern generation. ICCAD 2002: 87-93
- [c55]Janusz Rajski, Jerzy Tyszer, Mark Kassab, Nilanjan Mukherjee, Rob Thompson, Kun-Han Tsai, Andre Hertwig, Nagesh Tamarapalli, Grzegorz Mrugalski, Geir Eide, Jun Qian: Embedded Deterministic Test for Low-Cost Manufacturing Test. ITC 2002: 301-310
- [c54]Nadir Z. Basturkmen, Sudhakar M. Reddy, Janusz Rajski: Improved Algorithms for Constructive Multi-Phase Test Point Insertion for Scan Based BIST. VLSI Design 2002: 604-
- [c53]J. Borel, Anand Raghunathan, Jim Sproch, Michael Howells, Janusz Rajski: Innovations in Test Automation. VTS 2002: 43-46
- 2001
- [j28]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Testing Schemes for FIR Filter Structures. IEEE Trans. Computers 50(7): 674-688 (2001)
- [c52]
- [c51]John T. Chen, Jitendra Khare, Ken Walker, Saghir A. Shaikh, Janusz Rajski, Wojciech Maly: Test response compression and bitmap encoding for embedded memories in manufacturing process monitoring. ITC 2001: 258-267
- [c50]Xijiang Lin, Janusz Rajski, Irith Pomeranz, Sudhakar M. Reddy: On static test compaction and test pattern ordering for scan designs. ITC 2001: 1088-1097
- [c49]John T. Chen, Wojciech Maly, Janusz Rajski, Omar Kebichi, Jitendra Khare: Enabling Embedded Memory Diagnosis via Test Response Compression. VTS 2001: 292-298
- 2000
- [j27]Grzegorz Mrugalski, Janusz Rajski, Jerzy Tyszer: Cellular automata-based test pattern generators with phase shifters. IEEE Trans. on CAD of Integrated Circuits and Systems 19(8): 878-893 (2000)
- [j26]Kun-Han Tsai, Janusz Rajski, Malgorzata Marek-Sadowska: Star test: the theory and its applications. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1052-1064 (2000)
- [j25]Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer: Automated synthesis of phase shifters for built-in self-testapplications. IEEE Trans. on CAD of Integrated Circuits and Systems 19(10): 1175-1188 (2000)
- [c48]Xiaoliang Bai, Sujit Dey, Janusz Rajski: Self-test methodology for at-speed test of crosstalk in chip interconnects. DAC 2000: 619-624
- [c47]Yu Huang, Irith Pomeranz, Sudhakar M. Reddy, Janusz Rajski: Improving the Proportion of At-Speed Tests in Scan BIST. ICCAD 2000: 459-463
- [c46]Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski: Linear Independence as Evaluation Criterion for Two-Dimensional Test Pattern Generators. VTS 2000: 377-388
1990 – 1999
- 1999
- [j24]Janusz Rajski, Jerzy Tyszer: Diagnosis of Scan Cells in BIST Environment. IEEE Trans. Computers 48(7): 724-731 (1999)
- [c45]Graham Hetherington, Tony Fryars, Nagesh Tamarapalli, Mark Kassab, Abu S. M. Hassan, Janusz Rajski: Logic BIST for large industrial designs: real issues and case studies. ITC 1999: 358-367
- [c44]Grzegorz Mrugalski, Jerzy Tyszer, Janusz Rajski: Synthesis of pattern generators based on cellular automata with phase shifters. ITC 1999: 368-377
- [c43]Kuo-Hui Tsai, Tompson, Janusz Rajski, Malgorzata Marek-Sadowska: STAR-ATPG: a high speed test pattern generator for large scan designs. ITC 1999: 1021-1030
- [c42]Janusz Rajski, Jerzy Tyszer, Sanjay Patel: Built-In Self-Test for Systems on Silicon. VLSI Design 1999: 609-610
- [c41]Janusz Rajski, Grzegorz Mrugalski, Jerzy Tyszer: Comparative Study of CA-based PRPGs and LFSRs with Phase Shifters. VTS 1999: 236-245
- 1998
- [j23]Janusz Rajski, Jerzy Tyszer, Nadime Zacharia: Test Data Decompression for Multiple Scan Designs with Boundary Scan. IEEE Trans. Computers 47(11): 1188-1200 (1998)
- [c40]Aiman H. El-Maleh, Mark Kassab, Janusz Rajski: A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. DAC 1998: 625-631
- [c39]
- [c38]Janusz Rajski, Nagesh Tamarapalli, Jerzy Tyszer: Automated synthesis of large phase shifters for built-in self-test. ITC 1998: 1047-1056
- [c37]
- 1997
- [j22]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Design of Testable Multipliers for Fixed-Width Data Paths. IEEE Trans. Computers 46(7): 795-810 (1997)
- [j21]Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly: Behavior and testability preservation under the retiming transformation. IEEE Trans. on CAD of Integrated Circuits and Systems 16(5): 528-543 (1997)
- [j20]Katarzyna Radecka, Janusz Rajski, Jerzy Tyszer: Arithmetic built-in self-test for DSP cores. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1358-1369 (1997)
- [c36]Kun-Han Tsai, Sybille Hellebrand, Janusz Rajski, Malgorzata Marek-Sadowska: STARBIST: Scan Autocorrelated Random Pattern Generation. DAC 1997: 472-477
- [c35]Kun-Han Tsai, Malgorzata Marek-Sadowska, Janusz Rajski: Scan-Encoded Test Pattern Generation for BIST. ITC 1997: 548-556
- [c34]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Parameterizable Testing Scheme for FIR Filters. ITC 1997: 694-703
- [c33]
- [c32]J. Borel, M. Cecchini, C. Malipeddi, Janusz Rajski, Yervant Zorian: Systems On Silicon: Design and Test Challenges. VTS 1997: 184-185
- 1996
- [j19]Sanjay Gupta, Janusz Rajski, Jerzy Tyszer: Arithmetic Additive Generators of Pseudo-Exhaustive Test Patterns. IEEE Trans. Computers 45(8): 939-949 (1996)
- [j18]Janusz Rajski, Jerzy Tyszer: On Linear Dependencies in Subspaces of LFSR-Generated Sequences. IEEE Trans. Computers 45(10): 1212-1216 (1996)
- [j17]Thomas E. Marchok, Aiman H. El-Maleh, Wojciech Maly, Janusz Rajski: A complexity analysis of sequential ATPG. IEEE Trans. on CAD of Integrated Circuits and Systems 15(11): 1409-1423 (1996)
- [c31]Nadime Zacharia, Janusz Rajski, Jerzy Tyszer, John A. Waicukauski: Two-Dimensional Test Data Decompressor for Multiple Scan Designs. ITC 1996: 186-194
- [c30]Nagesh Tamarapalli, Janusz Rajski: Constructive Multi-Phase Test Point Insertion for Scan-Based BIST. ITC 1996: 649-658
- [c29]Fidel Muradali, Janusz Rajski: A self-driven test structure for pseudorandom testing of non-scan sequential circuits. VTS 1996: 17-25
- [c28]J. El-Ziq, Najmi T. Jarwala, Niraj K. Jha, Peter Marwedel, Christos A. Papachristou, Janusz Rajski, John W. Sheppard: Hardware-Software Co-Design for Test: It's the Last Straw! VTS 1996: 506-507
- 1995
- [j16]Thomas E. Marchok, Aiman H. El-Maleh, Janusz Rajski, Wojciech Maly: Testability Implications of Performance-Driven Logic Synthesis. IEEE Design & Test of Computers 12(2): 32-39 (1995)
- [j15]Sybille Hellebrand, Janusz Rajski, Steffen Tarnick, Srikanth Venkataraman, Bernard Courtois: Built-In Test for Circuits with Scan Based on Reseeding of Multiple-Polynomial Linear Feedback Shift Registers. IEEE Trans. Computers 44(2): 223-233 (1995)
- [j14]Aiman H. El-Maleh, Janusz Rajski: Delay-fault testability preservation of the concurrent decomposition and factorization transformations. IEEE Trans. on CAD of Integrated Circuits and Systems 14(5): 582-590 (1995)
- [c27]Aiman H. El-Maleh, Thomas E. Marchok, Janusz Rajski, Wojciech Maly: On Test Set Preservation of Retimed Circuits. DAC 1995: 176-182
- [c26]Mark Kassab, Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: Software Accelerated Functional Fault Simulation for Data-Path Architectures. DAC 1995: 333-338
- [c25]Nilanjan Mukherjee, Janusz Rajski, Jerzy Tyszer: On testable multipliers for fixed-width data path architectures. ICCAD 1995: 541-547
- [c24]Mark Kassab, Janusz Rajski, Jerzy Tyszer: Hierarchical Functional-Fault Simulation for High-Level Synthesis. ITC 1995: 596-605
- [c23]Nilanjan Mukherjee, H. Kassab, Janusz Rajski, Jerzy Tyszer: Arithmetic built-in self test for high-level synthesis. VTS 1995: 132-139
- [c22]
- [c21]Nadime Zacharia, Janusz Rajski, Jerzy Tyszer: Decompression of test data using variable-length seed LFSRs. VTS 1995: 426-433
- 1994
- [j13]Henry Cox, Janusz Rajski: On necessary and nonconflicting assignments in algorithmic test pattern generation. IEEE Trans. on CAD of Integrated Circuits and Systems 13(4): 515-530 (1994)
- [c20]Sanjay Gupta, Janusz Rajski, Jerzy Tyszer: Test pattern generation based on arithmetic operations. ICCAD 1994: 117-124
- [c19]Aiman El-Maleh, Janusz Rajski: Delay-fault testability preservation of the concurrent decomposition and factorization transformations. VTS 1994: 15-21
- 1993
- [j12]Janusz Rajski, Jerzy Tyszer: Accumulator-Based Compaction of Test Responses. IEEE Trans. Computers 42(6): 643-650 (1993)
- [j11]Janusz Rajski, Jerzy Tyszer: Recursive Pseudoexhaustive Test Pattern Generation. IEEE Trans. Computers 42(12): 1517-1521 (1993)
- [j10]Fadi Maamari, Janusz Rajski: The dynamic reduction of fault simulation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(1): 137-148 (1993)
- [j9]Janusz Rajski, Jerzy Tyszer: Test responses compaction in accumulators with rotate carry adders. IEEE Trans. on CAD of Integrated Circuits and Systems 12(4): 531-539 (1993)
- 1992
- [j8]Ashish Pancholy, Janusz Rajski, Larry J. McNaughton: Empirical Failure Analysis and Validation of Fault Models in CMOS VLSI Circuits. IEEE Design & Test of Computers 9(1): 72-83 (1992)
- [j7]Janusz Rajski, Jagadeesh Vasudevamurthy: The testability-preserving concurrent decomposition and factorization of Boolean expressions. IEEE Trans. on CAD of Integrated Circuits and Systems 11(6): 778-793 (1992)
- [j6]Abu S. M. Hassan, Vinod K. Agarwal, Benoit Nadeau-Dostie, Janusz Rajski: BIST of PCB interconnects using boundary-scan architecture. IEEE Trans. on CAD of Integrated Circuits and Systems 11(10): 1278-1288 (1992)
- [c18]Sybille Hellebrand, Steffen Tarnick, Bernard Courtois, Janusz Rajski: Generation of Vector Patterns Through Reseeding of Multipe-Polynominal Linear Feedback Shift Registers. ITC 1992: 120-129
- 1991
- [j5]Janusz Rajski, Jerzy Tyszer: On the diagnostic properties of linear feedback shift registers. IEEE Trans. on CAD of Integrated Circuits and Systems 10(10): 1316-1322 (1991)
- [c17]Stephen Pateras, Janusz Rajski: Generation of Correlated Random Patterns for the Complete Testing of Synthesized Multi-level Circuits. DAC 1991: 347-352
- [c16]Stephen Pateras, Janusz Rajski: Cube-Contained Random Patterns and Their Applications to the Complete Testing of Synthesized Multi-Level Circuits. ITC 1991: 473-482
- 1990
- [j4]Fadi Maamari, Janusz Rajski: A method of fault simulation based on stem regions. IEEE Trans. on CAD of Integrated Circuits and Systems 9(2): 212-220 (1990)
- [c15]Janusz Rajski, Jerzy Tyszer, Babak Salimi: On the Diagnostic Resolution of Signature Analysis. ICCAD 1990: 364-367
- [c14]Jagadeesh Vasudevamurthy, Janusz Rajski: A Method for Concurrent Decomposition and Factorization of Boolean Expressions. ICCAD 1990: 510-513
- [c13]
- [c12]Janusz Rajski, Jagadeesh Vasudevamurthy: Testability preserving transformations in multi-level logic synthesis. ITC 1990: 265-273
- [c11]
- [c10]Ashish Pancholy, Janusz Rajski, Larry J. McNaughton: Empirical failure analysis and validation of fault models in CMOS VLSI. ITC 1990: 938-947
1980 – 1989
- 1989
- [c9]Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski, Benoit Nadeau-Dostie: Testing of Glue Logic Interconnects Using Boundary Scan Architecture. ITC 1989: 700-711
- 1988
- [j3]Henry Cox, Janusz Rajski: A method of fault analysis for test generation and fault diagnosis. IEEE Trans. on CAD of Integrated Circuits and Systems 7(7): 813-833 (1988)
- [c8]Fadi Maamari, Janusz Rajski: A reconvergent fanout analysis for efficient exact fault simulation of combinational circuits. FTCS 1988: 122-127
- [c7]
- [c6]Abu S. M. Hassan, Vinod K. Agarwal, Janusz Rajski: Testing and Diagnosis of Interconnects Using Boundary Scan Architecture. ITC 1988: 126-137
- [c5]Henry Cox, André Ivanov, Vinod K. Agarwal, Janusz Rajski: On Multiple Fault Coverage and Aliasing Probability Measures. ITC 1988: 314-321
- [c4]
- [c3]Markus Robinson, Janusz Rajski: An Algorithmic Branch and Bound Method for PLA Test Pattern Generation. ITC 1988: 784-795
- 1986
- [j2]Janusz Rajski, Jerzy Tyszer: The Influence of Masking Phenomenon on Coverage Capability of Single Fault Test Sets in PLA's. IEEE Trans. Computers 35(1): 81-85 (1986)
- 1985
- [j1]Janusz Rajski, Jerzy Tyszer: Combinatorial Approach to Multiple Contact Faults Coverage in Programmable Logic Arrays. IEEE Trans. Computers 34(6): 549-553 (1985)
- [c2]Vinod K. Agarwal, Janusz Rajski: Testing Properties and Applications of Inverter-Free PLA's. ITC 1985: 500-507
- 1984
- [c1]Janusz Rajski, Jerzy Tyszer: The detection of small size multiple faults by single fault test sets n programmable logic arrays. Fehlertolerierende Rechensysteme 1984: 417-425
Coauthor Index
[j55] [c137] [c136] [c134] [c133] [j54] [j53] [j52] [j51] [c132] [c130] [c129] [c128] [c127] [c125] [j50] [j49] [c122] [c121] [c120] [j47] [c114] [c113] [c112] [c111] [c110] [j46] [j44] [c107] [c105] [j42] [j41] [j39] [c104] [c99] [j38] [c96] [c94] [c89] [j36] [c78] [c77] [c76] [j34] [j33] [c71] [c68] [c67] [j32] [j30] [j29] [c66] [c64] [c61] [c58] [c55] [j28] [j27] [j25] [c46] [j24] [c44] [c42] [c41] [j23] [c39] [c38] [c37] [j22] [j20] [c34] [c33] [j19] [j18] [c31] [c26] [c25] [c24] [c23] [c21] [c20] [j12] [j11] [j9] [j5] [c15] [j2] [j1] [c1]
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last updated on 2013-05-25 21:24 CEST by the dblp team