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 | 2012 | |
|---|---|---|
| c31 |      | Paolo Roberto Grassi, Vincenzo Rana, Ivan Beretta, Donatella Sciuto: B2IRS: A Technique to Reduce BAN-BAN Interferences in Wireless Sensor Networks. BSN 2012: 46-51 |
| c30 | | Paolo Roberto Grassi, Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto: Knowledge-based design space exploration of wireless sensor networks. CODES+ISSS 2012: 225-234 |
| c29 | | Ivan Beretta, Francisco J. Rincón, Nadia Khaled, Paolo Roberto Grassi, Vincenzo Rana, David Atienza: Design exploration of energy-performance trade-offs for wireless sensor networks. DAC 2012: 1043-1048 |
| c28 | | Paolo Roberto Grassi, Vincenzo Rana, Ivan Beretta, Donatella Sciuto: Tacit Consent: A Technique to Reduce Redundant Transmissions from Spatially Correlated Nodes in Wireless Sensor Networks. DSD 2012: 874-881 |
| 2011 | ||
| j2 | | Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto: Island-Based Adaptable Embedded System Design. Embedded Systems Letters 3(2): 53-57 (2011) |
| j1 | | Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto: A Mapping Flow for Dynamically Reconfigurable Multi-Core System-on-Chip Design. IEEE Trans. on CAD of Integrated Circuits and Systems 30(8): 1211-1224 (2011) |
| c27 | | Francesco Bruschi, Francesco Perini, Vincenzo Rana, Donatella Sciuto: An efficient Quantum-Dot Cellular Automata adder. DATE 2011: 1220-1223 |
| c26 | | A. Akin, Ivan Beretta, A. A. Nacci, Vincenzo Rana, Marco D. Santambrogio, David Atienza: A high-performance parallel implementation of the Chambolle algorithm. DATE 2011: 1436-1441 |
| c25 | | Juan Antonio Clemente, Vincenzo Rana, Donatella Sciuto, Ivan Beretta, David Atienza: A Hybrid Mapping-Scheduling Technique for Dynamically Reconfigurable Hardware. FPL 2011: 177-180 |
| c24 | | Francesco Bruschi, Antonio Miele, Vincenzo Rana: On-chip network resource management design and validation. ICSAMOS 2011: 249-254 |
| 2010 | ||
| c23 | | Marco D. Santambrogio, Vincenzo Rana, Ivan Beretta, Donatella Sciuto: Operating system runtime management of partially dynamically reconfigurable embedded systems. ESTImedia 2010: 1-10 |
| c22 | | Francesco Bruschi, Marco Paolieri, Vincenzo Rana: A Reconfigurable System Based on a Parallel and Pipelined Solution for Regular Expression Matching. FPL 2010: 44-49 |
| c21 | | Vincenzo Rana, Donatella Sciuto: A novel design framework for the design of reconfigurable systems based on NoCs. ACM Great Lakes Symposium on VLSI 2010: 1-2 |
| c20 | | Ivan Beretta, Vincenzo Rana, David Atienza, Donatella Sciuto: Run-time mapping of applications on FPGA-based reconfigurable systems. ISCAS 2010: 3329-3332 |
| 2009 | ||
| c19 | | Vincenzo Rana, Srinivasan Murali, David Atienza, Marco D. Santambrogio, Luca Benini, Donatella Sciuto: Minimization of the reconfiguration latency for the mapping of applications on FPGA-based systems. CODES+ISSS 2009: 325-334 |
| c18 | | Dario Cozzi, Claudia Farè, Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto: Reconfigurable NoC design flow for multiple applications run-time mapping on FPGA devices. ACM Great Lakes Symposium on VLSI 2009: 421-424 |
| c17 | | Ivan Beretta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto: On-line task management for a reconfigurable cryptographic architecture. IPDPS 2009: 1-4 |
| 2008 | ||
| c16 | | Carlo Curino, Luca Fossati, Vincenzo Rana, Francesco Redaelli, Marco D. Santambrogio, Donatella Sciuto: The Shining embedded system design methodology based on self dynamic reconfigurable architectures. ASP-DAC 2008: 595-600 |
| c15 | | Andrea Cuoccio, Paolo Roberto Grassi, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto: A Generation Flow for Self-Reconfiguration Controllers Customization. DELTA 2008: 279-284 |
| c14 | | Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto: A Requirements-Driven Reconfigurable SoC Communication Infrastructure Design Flow. DELTA 2008: 405-409 |
| c13 | | Vincenzo Rana, Matteo Matteucci, Daniele Caltabiano, Roberto Sannino, Andrea Bonarini: Low cost smartcams design. ESTImedia 2008: 27-32 |
| c12 | | Francesco Bruschi, Vincenzo Rana, Donatella Sciuto: An architecture for dynamically reconfigurable real time audio processing systems. ESTImedia 2008: 81-86 |
| c11 | | Alessandro Meroni, Vincenzo Rana, Marco D. Santambrogio, Francesco Bruschi: A Requirements-Driven Simulation Framework for Communication Infrastructures Design. FDL 2008: 111-117 |
| c10 | | Marco D. Santambrogio, Vincenzo Rana, Donatella Sciuto: Operating system support for online partial dynamic reconfiguration management. FPL 2008: 455-458 |
| c9 | | Alessio Montone, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto: HARPE: A Harvard-based processing element tailored for partial dynamic reconfigurable architectures. IPDPS 2008: 1-8 |
| c8 | | Simone Corbetta, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto: A light-weight Network-on-Chip architecture for dynamically reconfigurable systems. ICSAMOS 2008: 49-56 |
| 2007 | ||
| c7 | | Marco D. Santambrogio, Seda Ogrenci Memik, Vincenzo Rana, Umut A. Acar, Donatella Sciuto: A novel SoC design methodology combining adaptive software and reconfigurable hardware. ICCAD 2007: 303-308 |
| c6 | | Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto, Boris Kettelhoit, Markus Köster, Mario Porrmann, Ulrich Rückert: Partial Dynamic Reconfiguration in a Multi-FPGA Clustered Architecture Based on Linux. IPDPS 2007: 1-8 |
| c5 | | Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto: Dynamic Reconfigurability in Embedded System Design. ISCAS 2007: 2734-2737 |
| c4 | | Vincenzo Rana, Chiara Sandionigi, Marco D. Santambrogio, Donatella Sciuto: An adaptive genetic algorithm for dynamically reconfigurable modules allocation. VLSI-SoC 2007: 128-133 |
| 2006 | ||
| c3 | | Vincenzo Rana, Marco D. Santambrogio, Seda Ogrenci Memik, Donatella Sciuto: Combining hardware reconfiguration and adaptive computation for a novel SoC design methodology. FPT 2006: 293-296 |
| c2 | | Fabrizio Ferrandi, G. Ferrara, R. Palazzo, Vincenzo Rana, Marco D. Santambrogio: VHDL to FPGA automatic IP-Core generation: a case study on Xilinx design flow. IPDPS 2006 |
| c1 | | Matteo Murgida, Alessandro Panella, Vincenzo Rana, Marco D. Santambrogio, Donatella Sciuto: Fast IP-Core Generation in a Partial Dynamic Reconfiguration Workflow. VLSI-SoC 2006: 74-79 |
Colors in the list of coauthors
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