Nagarajan Ranganathan
List of publications from the DBLP Bibliography Server - FAQ
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 | 2013 | |
|---|---|---|
| j67 |      | Ransford Hyman Jr., Nagarajan Ranganathan, Thomas Bingel, Deanne Tran Vo: A Clock Control Strategy for Peak Power and RMS Current Reduction Using Path Clustering. IEEE Trans. VLSI Syst. 21(2): 259-269 (2013) |
| 2012 | ||
| j66 | | Venkataraman Mahalingam, Nagarajan Ranganathan, Ransford Hyman Jr.: Dynamic clock stretching for variation compensation in VLSI circuit design. JETC 8(3): 16 (2012) |
| c116 | | Yue Wang, Soumyaroop Roy, Nagarajan Ranganathan: Run-time power-gating in caches of GPUs for leakage energy savings. DATE 2012: 300-303 |
| c115 | | Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan: Mach-Zehnder interferometer based design of all optical reversible binary adder. DATE 2012: 721-726 |
| c114 | | Himanshu Thapliyal, Nagarajan Ranganathan: Design, Synthesis and Test of Reversible Circuits for Emerging Nanotechnologies. ISVLSI 2012: 5-6 |
| c113 | | Saurabh Kotiyal, Himanshu Thapliyal, Nagarajan Ranganathan: Mach-Zehnder Interferometer Based All Optical Reversible NOR Gates. ISVLSI 2012: 207-212 |
| c112 | | Matthew Morrison, Nagarajan Ranganathan: Analysis of Reversible Logic Based Sequential Computing Structures Using Quantum Mechanics Principles. ISVLSI 2012: 219-224 |
| c111 | | Matthew Morrison, Matthew Lewandowski, Nagarajan Ranganathan: Design of a Tree-Based Comparator and Memory Unit Based on a Novel Reversible Logic Structure. ISVLSI 2012: 231-236 |
| c110 | | Himanshu Thapliyal, Nagarajan Ranganathan: Tutorial T2: Reversible Logic: Fundamentals and Applications in Ultra-Low Power, Fault Testing and Emerging Nanotechnologies, and Challenges in Future. VLSI Design 2012: 13-15 |
| 2011 | ||
| j65 | | Ransford Hyman Jr., Koustav Bhattacharya, Nagarajan Ranganathan: Redundancy Mining for Soft Error Detection in Multicore Processors. IEEE Trans. Computers 60(8): 1114-1125 (2011) |
| j64 | | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori: State-Retentive Power Gating of Register Files in Multicore Processors Featuring Multithreaded In-Order Cores. IEEE Trans. Computers 60(11): 1547-1560 (2011) |
| j63 | | Koustav Bhattacharya, N. Ranganathan: Placement for Immunity of Transient Faults in Cell-Based Design of Nanometer Circuits. IEEE Trans. VLSI Syst. 19(5): 918-923 (2011) |
| j62 | | Upavan Gupta, Nagarajan Ranganathan: A Utilitarian Approach to Variation Aware Delay, Power, and Crosstalk Noise Optimization. IEEE Trans. VLSI Syst. 19(9): 1723-1726 (2011) |
| c109 | | |
| c108 | | |
| c107 | | Matthew Morrison, Nagarajan Ranganathan: Design of a Reversible ALU Based on Novel Programmable Reversible Logic Gate Structures. ISVLSI 2011: 126-131 |
| i1 | | Himanshu Thapliyal, Nagarajan Ranganathan: Reversible Logic Based Concurrent Error Detection Methodology For Emerging Nanocircuits. CoRR abs/1101.4222 (2011) |
| 2010 | ||
| j61 | | Himanshu Thapliyal, Nagarajan Ranganathan: Design of reversible sequential circuits optimizing quantum cost, delay, and garbage outputs. JETC 6(4): 14 (2010) |
| j60 | | Upavan Gupta, Nagarajan Ranganathan: A Game Theoretic Approach for Simultaneous Compaction and Equipartitioning of Spatial Data Sets. IEEE Trans. Knowl. Data Eng. 22(4): 465-478 (2010) |
| j59 | | Venkataraman Mahalingam, Koustav Bhattacharya, N. Ranganathan, Hari Chakravarthula, Robin R. Murphy, Kevin S. Pratt: A VLSI Architecture and Algorithm for Lucas-Kanade-Based Optical Flow Computation. IEEE Trans. VLSI Syst. 18(1): 29-38 (2010) |
| j58 | | Venkataraman Mahalingam, N. Ranganathan: Timing-Based Placement Considering Uncertainty Due to Process Variations. IEEE Trans. VLSI Syst. 18(6): 1007-1011 (2010) |
| c106 | | Himanshu Thapliyal, Nagarajan Ranganathan: Design of Reversible Latches Optimized for Quantum Cost, Delay and Garbage Outputs. VLSI Design 2010: 235-240 |
| 2009 | ||
| j57 | | Nagarajan Ranganathan, Upavan Gupta, Venkataraman Mahalingam: Variation-aware multimetric optimization during gate sizing. ACM Trans. Design Autom. Electr. Syst. 14(4) (2009) |
| j56 | | Koustav Bhattacharya, Nagarajan Ranganathan, Soontae Kim: A Framework for Correction of Multi-Bit Soft Errors in L2 Caches Based on Redundancy. IEEE Trans. VLSI Syst. 17(2): 194-206 (2009) |
| j55 | | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori: A Framework for Power-Gating Functional Units in Embedded Microprocessors. IEEE Trans. VLSI Syst. 17(11): 1640-1649 (2009) |
| c105 | | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori: Compiler-directed leakage reduction in embedded microprocessors. ICCD 2009: 35-40 |
| c104 | | Koustav Bhattacharya, Venkataraman Mahalingam, Nagarajan Ranganathan: A VLSI System Architecture for Optical Flow Computation. ISCAS 2009: 357-360 |
| c103 | | Soumyaroop Roy, Nagarajan Ranganathan, Srinivas Katkoori: Exploring Compiler Optimizations for Enhancing Power Gating. ISCAS 2009: 1004-1007 |
| c102 | | Himanshu Thapliyal, Nagarajan Ranganathan: Concurrently Testable FPGA Design for Molecular QCA using Conservative Reversible Logic Gate. ISCAS 2009: 1815-1818 |
| c101 | | Ransford Hyman Jr., Koustav Bhattacharya, N. Ranganathan: A Strategy for Soft Error Reduction in Multi Core Designs. ISCAS 2009: 2217-2220 |
| c100 | | Koustav Bhattacharya, Nagarajan Ranganathan: A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. ISQED 2009: 388-393 |
| c99 | | Koustav Bhattacharya, Nagarajan Ranganathan: A New Placement Algorithm for Reduction of Soft Errors in Macrocell Based Design of Nanometer Circuits. ISVLSI 2009: 91-96 |
| c98 | | Himanshu Thapliyal, Nagarajan Ranganathan: Design of Efficient Reversible Binary Subtractors Based on a New Reversible Gate. ISVLSI 2009: 229-234 |
| c97 | | Koustav Bhattacharya, Nagarajan Ranganathan: RADJAM: A Novel Approach for Reduction of Soft Errors in Logic Circuits. VLSI Design 2009: 453-458 |
| c96 | | Himanshu Thapliyal, Nagarajan Ranganathan: Conservative QCA Gate (CQCA) for Designing Concurrently Testable Molecular QCA Circuits. VLSI Design 2009: 511-516 |
| 2008 | ||
| j54 | | Venkataraman Mahalingam, N. Ranganathan, J. E. Harlow: A Fuzzy Optimization Approach for Variation Aware Power Minimization During Gate Sizing. IEEE Trans. VLSI Syst. 16(8): 975-984 (2008) |
| c95 | | N. Ranganathan, Upavan Gupta, Venkataraman Mahalingam: Simultaneous optimization of total power, crosstalk noise, and delay under uncertainty. ACM Great Lakes Symposium on VLSI 2008: 171-176 |
| c94 | | Koustav Bhattacharya, Nagarajan Ranganathan: A linear programming formulation for security-aware gate sizing. ACM Great Lakes Symposium on VLSI 2008: 273-278 |
| c93 | | Upavan Gupta, Nagarajan Ranganathan: A microeconomic approach to multi-objective spatial clustering. ICPR 2008: 1-4 |
| c92 | | Upavan Gupta, Nagarajan Ranganathan: An expected-utility based approach to variation aware VLSI optimization under scarce information. ISLPED 2008: 81-86 |
| c91 | | Koustav Bhattacharya, Nagarajan Ranganathan: Reliability-centric gate sizing with simultaneous optimization of soft error rate, delay and power. ISLPED 2008: 99-104 |
| c90 | | Venkataraman Mahalingam, Nagarajan Ranganathan: A Fuzzy Approach for Variation Aware Buffer Insertion and Driver Sizing. ISVLSI 2008: 329-334 |
| 2007 | ||
| j53 | | Saraju P. Mohanty, Elias Kougianos, Nagarajan Ranganathan: VLSI architecture and chip for combined invisible robust and fragile watermarking. IET Computers & Digital Techniques 1(5): 600-611 (2007) |
| j52 | | K. P. Subbalakshmi, Rajarathnam Chandramouli, Nagarajan Ranganathan: A Sequential Distinguisher for Covert Channel Identification. I. J. Network Security 5(3): 274-282 (2007) |
| j51 | | Upavan Gupta, Nagarajan Ranganathan: Multievent Crisis Management Using Noncooperative Multistep Games. IEEE Trans. Computers 56(5): 577-589 (2007) |
| c89 | | Koustav Bhattacharya, Soontae Kim, Nagarajan Ranganathan: Improving the reliability of on-chip L2 cache using redundancy. ICCD 2007: 224-229 |
| c88 | | Upavan Gupta, Nagarajan Ranganathan: A microeconomic approach to multi-robot team formation. IROS 2007: 3019-3024 |
| c87 | | Venkataraman Mahalingam, N. Ranganathan: Variation Aware Timing Based Placement Using Fuzzy Programming. ISQED 2007: 327-332 |
| c86 | | Narender Hanchate, Nagarajan Ranganathan: Integrated Gate and Wire Sizing at Post Layout Level. ISVLSI 2007: 225-232 |
| c85 | | Narender Hanchate, Nagarajan Ranganathan: Statistical Gate Sizing for Yield Enhancement at Post Layout Level. ISVLSI 2007: 245-252 |
| c84 | | Soumyaroop Roy, Srinivas Katkoori, Nagarajan Ranganathan: A Compiler Based Leakage Reduction Technique by Power-Gating Functional Units in Embedded Microprocessors. VLSI Design 2007: 215-220 |
| 2006 | ||
| j50 | | Narender Hanchate, Nagarajan Ranganathan: Simultaneous Interconnect Delay and Crosstalk Noise Optimization through Gate Sizing Using Game Theory. IEEE Trans. Computers 55(8): 1011-1023 (2006) |
| j49 | | Venkataraman Mahalingam, Nagarajan Ranganathan: Improving Accuracy in Mitchell's Logarithmic Multiplication Using Operand Decomposition. IEEE Trans. Computers 55(12): 1523-1535 (2006) |
| j48 | | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: ILP models for simultaneous energy and transient power minimization during behavioral synthesis. ACM Trans. Design Autom. Electr. Syst. 11(1): 186-212 (2006) |
| j47 | | Narender Hanchate, Nagarajan Ranganathan: A game-theoretic framework for multimetric optimization of interconnect delay, power, and crosstalk noise during wire sizing. ACM Trans. Design Autom. Electr. Syst. 11(3): 711-739 (2006) |
| j46 | | Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan: A stimulus-free graphical probabilistic switching model for sequential circuits using dynamic bayesian networks. ACM Trans. Design Autom. Electr. Syst. 11(3): 773-796 (2006) |
| c83 | | Venkataraman Mahalingam, N. Ranganathan, Justin E. Harlow III: A novel approach for variation aware power minimization during gate sizing. ISLPED 2006: 174-179 |
| c82 | | Narender Hanchate, Nagarajan Ranganathan: Post-Layout Gate Sizing for Interconnect Delay and Crosstalk Noise Optimization. ISQED 2006: 92-97 |
| c81 | | Nagarajan Ranganathan, Ravi Namballa, Narender Hanchate: CHESS: A Comprehensive Tool for CDFG Extraction and Synthesis of Low Power Designs from VHDL. ISVLSI 2006: 329-334 |
| c80 | | Narender Hanchate, Nagarajan Ranganathan: A Linear Time Algorithm for Wire Sizing with Simultaneous Optimization of Interconnect Delay and Crosstalk Noise. VLSI Design 2006: 283-290 |
| c79 | | Venkataraman Mahalingam, N. Ranganathan: An Efficient and Accurate Logarithmic Multiplier Based on Operand Decomposition. VLSI Design 2006: 393-398 |
| c78 | | Viswanath Sairaman, Nagarajan Ranganathan, Neeta S. Singh: An Automatic Code Generation Tool for Partitioned Software in Distributed Systems. VLSI Design 2006: 477-480 |
| c77 | | Aswath Oruganti, Nagarajan Ranganathan: Leakage Power Reduction in Dual-Vdd and Dual-Vth Designs through Probabilistic Analysis of Vth Variation. VLSI Design 2006: 766-769 |
| 2005 | ||
| j45 | | Saraju P. Mohanty, N. Ranganathan: Energy-efficient datapath scheduling using multiple voltages and dynamic clocking. ACM Trans. Design Autom. Electr. Syst. 10(2): 330-353 (2005) |
| j44 | | Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: A VLSI architecture for watermarking in a secure still digital camera (S/sup 2/DC) design. IEEE Trans. VLSI Syst. 13(7): 808-818 (2005) |
| j43 | | Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: A VLSI architecture for visible watermarking in a secure still digital camera (S/sup 2/DC) design (Corrected)*. IEEE Trans. VLSI Syst. 13(8): 1002-1012 (2005) |
| c76 | | Venkataraman Mahalingam, N. Ranganathan: A Nonlinear Programming Based Power Optimization Methodology for Gate Sizing and Voltage Selection. ISVLSI 2005: 180-185 |
| c75 | | Saraju P. Mohanty, N. Ranganathan, K. Balakrishnan: Design of a Low Power Image Watermarking Encoder Using Dual Voltage and Frequency. VLSI Design 2005: 153-158 |
| c74 | | Sanjukta Bhanja, Karthikeyan Lingasubramanian, N. Ranganathan: Estimation of Switching Activity in Sequential Circuits Using Dynamic Bayesian Networks. VLSI Design 2005: 586-591 |
| 2004 | ||
| j42 | | Ramamurti Chandramouli, Koduvayur P. Subbalakshmi, N. Ranganathan: Stochastic channel-adaptive rate control for wireless video transmission. Pattern Recognition Letters 25(7): 793-806 (2004) |
| j41 |  | |
| j40 | | Narender Hanchate, Nagarajan Ranganathan: LECTOR: a technique for leakage reduction in CMOS circuits. IEEE Trans. VLSI Syst. 12(2): 196-205 (2004) |
| j39 | | Saraju P. Mohanty, Nagarajan Ranganathan: A framework for energy and transient power reduction during behavioral synthesis. IEEE Trans. VLSI Syst. 12(6): 562-572 (2004) |
| j38 | | Sanjukta Bhanja, N. Ranganathan: Cascaded Bayesian inferencing for switching activity estimation with correlated inputs. IEEE Trans. VLSI Syst. 12(12): 1360-1370 (2004) |
| c73 | | Ravi Namballa, Nagarajan Ranganathan, Abdel Ejnioui: Control and Data Flow Graph Extraction for High-Level Synthesis. ISVLSI 2004: 192 |
| c72 | | Ashok K. Murugavel, N. Ranganathan: Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. VLSI Design 2004: 195-200 |
| c71 | | Narender Hanchate, Nagarajan Ranganathan: A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. VLSI Design 2004: 228-233 |
| c70 | | Ashok K. Murugavel, N. Ranganathan: Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. VLSI Design 2004: 670- |
| c69 | | Saraju P. Mohanty, Nagarajan Ranganathan, Sunil K. Chappidi: ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. VLSI Design 2004: 745-748 |
| c68 | | Saraju P. Mohanty, Nagarajan Ranganathan, Ravi Namballa: VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. VLSI Design 2004: 1063- |
| 2003 | ||
| j37 | | Abdel Ejnioui, N. Ranganathan: Multiterminal net routing for partial crossbar-based multi-FPGA systems. IEEE Trans. VLSI Syst. 11(1): 71-78 (2003) |
| j36 | | Abdel Ejnioui, N. Ranganathan: Routing on field-programmable switch matrices. IEEE Trans. VLSI Syst. 11(2): 283-287 (2003) |
| j35 | | Sanjukta Bhanja, N. Ranganathan: Switching activity estimation of VLSI circuits using Bayesian networks. IEEE Trans. VLSI Syst. 11(4): 558-567 (2003) |
| j34 | | Ashok K. Murugavel, N. Ranganathan: Petri net modeling of gate and interconnect delays for power estimation. IEEE Trans. VLSI Syst. 11(5): 921-927 (2003) |
| j33 | | Ashok K. Murugavel, N. Ranganathan: A game theoretic approach for power optimization during behavioral synthesis. IEEE Trans. VLSI Syst. 11(6): 1031-1043 (2003) |
| c67 | | N. Ranganathan, Ashok K. Murugavel: A low power scheduler using game theory. CODES+ISSS 2003: 126-131 |
| c66 | | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Simultaneous peak and average power minimization during datapath scheduling for DSP processors. ACM Great Lakes Symposium on VLSI 2003: 215-220 |
| c65 | | N. Ranganathan, Ashok K. Murugavel: A Microeconomic Model for Simultaneous Gate Sizing and Voltage Scaling for Power Optimization. ICCD 2003: 276-281 |
| c64 | | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Power Fluctuation Minimization During Behavioral Synthesis using ILP-Based Datapath Scheduling. ICCD 2003: 441-443 |
| c63 | | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: An ILP-based scheduling scheme for energy efficient high performance datapath synthesis. ISCAS (5) 2003: 313-316 |
| c62 | | Saraju P. Mohanty, N. Ranganathan, Sunil K. Chappidi: Peak Power Minimization Through Datapath Scheduling. ISVLSI 2003: 121-126 |
| c61 | | Saraju P. Mohanty, N. Ranganathan: Energy Efficient Scheduling for Datapath Synthesis. VLSI Design 2003: 446-451 |
| c60 | | Ashok K. Murugavel, N. Ranganathan: A Game-Theoretic Approach for Binding in Behavioral Synthesis. VLSI Design 2003: 452- |
| c59 | | Saraju P. Mohanty, N. Ranganathan: A Framework for Energy and Transient Power Reduction during Behavioral Synthesis. VLSI Design 2003: 539-545 |
| 2002 | ||
| j32 | | Hitoshi Oi, N. Ranganathan: A comparative study of bidirectional ring and crossbar interconnection networks. Computers & Electrical Engineering 28(1): 43-57 (2002) |
| j31 | | Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali: Least-square estimation of average power in digital CMOS circuits. IEEE Trans. VLSI Syst. 10(1): 55-58 (2002) |
| c58 | | K. Sitaraman, N. Ranganathan, Abdel Ejnioui: A VLSI Architecture for Object Recognition Using Tree Matching. ASAP 2002: 325-334 |
| c57 | | Ashok K. Murugavel, N. Ranganathan: Petri net modeling of gate and interconnect delays for power estimation. DAC 2002: 455-460 |
| c56 | | Sanjukta Bhanja, N. Ranganathan: Modeling Switching Activity Using Cascaded Bayesian Networks for Correlated Input Streams. ICCD 2002: 388-390 |
| c55 | | Ashok K. Murugavel, N. Ranganathan: Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. ISLPED 2002: 267-270 |
| c54 | | Saraju P. Mohanty, N. Ranganathan, Vamsi Krishna: Datapath Scheduling using Dynamic Frequency Clocking. ISVLSI 2002: 65-70 |
| c53 | | Ashok K. Murugavel, N. Ranganathan: A Real Delay Switching Activity Simulator Based on Petri Net Modeling. VLSI Design 2002: 181-186 |
| c52 | | Sanjukta Bhanja, N. Ranganathan: Switching Activity Estimation of Large Circuits using Multiple Bayesian Networks. VLSI Design 2002: 187-192 |
| 2001 | ||
| j30 | | Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan: Context-based lossless image coding using EZW framework. IEEE Trans. Circuits Syst. Video Techn. 11(4): 554-559 (2001) |
| j29 | | N. Ranganathan, Minesh I. Patel, R. Sathyamurthy: An intelligent system for failure detection and control in an autonomous underwater vehicle. IEEE Transactions on Systems, Man, and Cybernetics, Part A 31(6): 762-767 (2001) |
| j28 | | Abdel Ejnioui, N. Ranganathan: A partitioning algorithm for technoiogy-mapped designs on single-chip emulation systems. IEEE Trans. VLSI Syst. 9(2): 407-410 (2001) |
| c51 | | Sanjukta Bhanja, N. Ranganathan: Dependency Preserving Probabilistic Modeling of Switching Activity using Bayesian Networks. DAC 2001: 209-214 |
| c50 | | Ashok K. Murugavel, N. Ranganathan, Ramamurti Chandramouli, Srinath Chavali: Average Power in Digital CMOS Circuits using Least Square Estimation. VLSI Design 2001: 215-220 |
| 2000 | ||
| j27 | | Girish Chiruvolu, Ravi Sankar, Nagarajan Ranganathan: VBR video traffic management using a predictor-based architecture. Computer Communications 23(1): 62-70 (2000) |
| j26 | | Hitoshi Oi, N. Ranganathan: Utilization of cache area in on-chip multiprocessor. Microprocessors and Microsystems - Embedded Hardware Design 24(8): 429-436 (2000) |
| c49 | | Raju D. Venkataramana, N. Ranganathan: New Cost Metrics for Iterative Task Assignment Algorithms in Heterogeneous Computing Systems. Heterogeneous Computing Workshop 2000: 160-167 |
| c48 | | Vamsi K. Srikantam, N. Ranganathan, Srikanth Srinivasan: CREAM: Combined Register and Module Assignment with Floorplanning for Low Power Datapath Synthesis. VLSI Design 2000: 228-233 |
| c47 | | Abdel Ejnioui, N. Ranganathan: Design Partitioning on Single-Chip Emulation Systems. VLSI Design 2000: 234-239 |
| c46 | | Abdel Ejnioui, N. Ranganathan: Routing on Switch Matrix Multi-FPGA Systems. VLSI Design 2000: 248-253 |
| 1999 | ||
| j25 | | Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan: Computation of lower bounds for switching activity using decision theory. IEEE Trans. VLSI Syst. 7(1): 125-129 (1999) |
| j24 | | Vamsi Krishna, N. Ranganathan, Abdel Ejnioui: A tree-matching chip. IEEE Trans. VLSI Syst. 7(2): 277-280 (1999) |
| c45 | | Narayanan Vijaykrishnan, N. Ranganathan: Tuning Branch Predictors to Support Virtual Method Invocation in Java. COOTS 1999: 217-228 |
| c44 | | Abdel Ejnioui, N. Ranganathan: Multi-Terminal Net Routing for Partial Crossbar-Based Multi-FPGA Systems. FPGA 1999: 176-185 |
| c43 | | Raju D. Venkataramana, N. Ranganathan: Multiple Cost Optimization for Task Assignment in Heterogeneous Computing Systems Using Learning Automata. Heterogeneous Computing Workshop 1999: 137-145 |
| c42 | | Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan: Context based lossless intraframe coding of video sequence using embedded zerotree wavelets. ISCAS (4) 1999: 323-326 |
| c41 | | Hitoshi Oi, N. Ranganathan: Utilization of Cache Area in On-Chip Multiprocessor. ISHPC 1999: 373-380 |
| c40 | | Raju D. Venkataramana, N. Ranganathan: A Learning Automata Based Framework for Task Assignment in Heterogeneous Computing Systems. SAC 1999: 541-547 |
| c39 | | Vamsi Krishna, N. Ranganathan, Narayanan Vijaykrishnan: Energy Efficient Datapath Synthesis Using Dynamic Frequency Clocking and Multiple Voltages. VLSI Design 1999: 440- |
| 1998 | ||
| j23 | | Girish Chiruvolu, Ravi Sankar, N. Ranganathan: Adaptive VBR video traffic management for higher utilization of ATM networks. Computer Communication Review 28(3): 27-40 (1998) |
| j22 | | |
| j21 | | N. Ranganathan, Raghu Sastry, R. Venkatesan: SMAC: A VLSI Architecture for Scene Matching. Real-Time Imaging 4(3): 171-180 (1998) |
| j20 | | Raghu Sastry, N. Ranganathan: A VLSI Architecture for Approximate Tree Matching. IEEE Trans. Computers 47(3): 346-352 (1998) |
| j19 | | Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss: Adaptive quantization and fast error-resilient entropy coding for image transmission. IEEE Trans. Circuits Syst. Video Techn. 8(4): 411-421 (1998) |
| j18 | | Nagarajan Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar: A linear array processor with dynamic frequency clocking for image processing applications. IEEE Trans. Circuits Syst. Video Techn. 8(4): 435-445 (1998) |
| c38 | | Ramamurti Chandramouli, N. Ranganathan, Shivaraman J. Ramadoss: Empirical Channel Matched Quantizer Design and UEP for Robust Image Transmission. Data Compression Conference 1998: 531 |
| c37 | | Narayanan Vijaykrishnan, N. Ranganathan, Ravi Gadekarla: Object-Oriented Architectural Support for a Java Processor. ECOOP 1998: 330-354 |
| c36 | | Vamsi Krishna, N. Ranganathan: A Methodology for High Level Power Estimation and Exploration. Great Lakes Symposium on VLSI 1998: 420-425 |
| c35 | | Raju D. Venkataramana, N. Ranganathan: A simple adaptive wormhole routing algorithm for MIMD systems. ICCD 1998: 205-207 |
| c34 | | Ramamurti Chandramouli, Sharad Kumar, N. Ranganathan: Joint Optimization of Quantization and On-Line Channel Estimation for Low Bit-Rate Video Transmission. ICIP (1) 1998: 649-653 |
| c33 | | Vamsi Krishna, Ramamurti Chandramouli, N. Ranganathan: Computation of Lower and Upper Bounds for Switching Activity: A Unified Approach. VLSI Design 1998: 230-233 |
| c32 | | Nagarajan Ranganathan, Rajat Anand, Girish Chiruvolu: A VLSI ATM Switch Architecture for VBR Traffic. VLSI Design 1998: 420-427 |
| 1997 | ||
| c31 | | Hitoshi Oi, N. Ranganathan: Effect of Message Length and Processor Speed on the Performance of the Bidirectional Ring-Based Multiprocessor. ICCD 1997: 267-272 |
| c30 | | Veeru N. Ramaswamy, Kameswara Rao Namuduri, N. Ranganathan: Performance Analysis of Wavelets in Embedded Zerotree-Based Lossless Image Coding Schemes. ICIP (2) 1997: 278-281 |
| c29 | | Ashley Rasquinha, N. Ranganathan: C3L: A Chip for Connected Component Labeling. VLSI Design 1997: 446-450 |
| 1996 | ||
| c28 | | Minesh I. Patel, N. Ranganathan: A VLSI System Architecture For Real-Time Intelligent Decision Making. ASAP 1996: 221-230 |
| c27 | | N. Ranganathan, Narayanan Vijaykrishnan, N. Bhavanishankar: A VLSI array architecture with dynamic frequency clocking. ICCD 1996: 137-140 |
| c26 | | S. B. Aruru, N. Ranganathan, Kameswara Rao Namuduri: A VLSI chip for image compression using variable block size segmentation. ICCD 1996: 500-505 |
| c25 | | Narayanan Vijaykrishnan, Nagarajan Ranganathan, N. Bhavanishankar: DFLAP: a dynamic frequency linear array processor. ICIP (2) 1996: 1007-1010 |
| c24 | | |
| c23 | | Narayanan Vijaykrishnan, N. Ranganathan: SUBGEN: a genetic approach for subcircuit extraction. VLSI Design 1996: 343-345 |
| 1995 | ||
| j17 | | N. Ranganathan, Sharad C. Seth: Conference Reports. IEEE Design & Test of Computers 12(2): 5, 81 (1995) |
| j16 | | |
| j15 | | Raghu Sastry, N. Ranganathan, Klinton Remedios: CASM: A VLSI Chip for Approximate String Matching. IEEE Trans. Pattern Anal. Mach. Intell. 17(8): 824-830 (1995) |
| j14 | | Raghu Sastry, N. Ranganathan, Ramesh Jain: VLSI Architectures for High-Speed Range Estimation. IEEE Trans. Pattern Anal. Mach. Intell. 17(9): 894-899 (1995) |
| j13 | | Nagarajan Ranganathan, Steve G. Romaniuk, Kameswara Rao Namuduri: A lossless image compression algorithm using variable block size segmentation. IEEE Transactions on Image Processing 4(10): 1396-1406 (1995) |
| j12 | | Nagarajan Ranganathan, Rajiv Mehrotra, S. Subramaniam: A high speed systolic architecture for labeling connected components in an image. IEEE Transactions on Systems, Man, and Cybernetics 25(3): 415-423 (1995) |
| c22 | | N. Ranganathan, K. B. Doreswamy: A systolic algorithm and architecture for image thinning. Great Lakes Symposium on VLSI 1995: 138-143 |
| c21 | | Raghu Sastry, N. Ranganathan: A VLSI Architecture for Computer the Tree-to-Tree Distance. HPCA 1995: 330-339 |
| c20 | | |
| c19 | | Mario Kovac, N. Ranganathan: JAGUAR: a high speed VLSI chip for JPEG image compression standard. VLSI Design 1995: 220-224 |
| 1994 | ||
| j11 | | |
| j10 | | Ken Hughes, N. Ranganathan: Modeling Sensor Confidence for Sensor Integration Tasks. IJPRAI 8(6): 1301-1318 (1994) |
| j9 | | Kameswara Rao Namuduri, Rajiv Mehrotra, Nagarajan Ranganathan: Efficient computation of gabor filter based multiresolution responses. Pattern Recognition 27(7): 925-938 (1994) |
| c18 | | |
| c17 | | N. Ranganathan, Satish Venugopal: An Efficient VLSI Architecture for Template Matching. ICPP (1) 1994: 224-231 |
| c16 | | N. Ranganathan, Bharadwaj Parthasarathy, Ken Hughes: A Parallel Algorithm and Architecture for Robot Path Planning. IPPS 1994: 275-279 |
| c15 | | Mario Kovac, N. Ranganathan: ACE: A VLSI Chip for Galois Field GF (2m) Based Exponentiation. VLSI Design 1994: 291-296 |
| 1993 | ||
| j8 | | Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: a VLSI systolic array implementation of a Galois field GF(2 m) based multiplication and division algorithm. IEEE Trans. VLSI Syst. 1(1): 22-30 (1993) |
| j7 | | Amar Mukherjee, N. Ranganathan, Jeffrey W. Flieder, Tinku Acharya: MARVLE: a VLSI chip for data compression using tree-based codes. IEEE Trans. VLSI Syst. 1(2): 203-214 (1993) |
| j6 | | Raghu Sastry, N. Ranganathan, Horst Bunke: VLSI architectures for polygon recognition. IEEE Trans. VLSI Syst. 1(4): 398-407 (1993) |
| c14 | | N. Ranganathan, Raghu Sastry, R. Venkatesan, Joseph W. Yoder, David C. Keezer: SMAC: A Scene Matching Chip. ICCD 1993: 184-187 |
| c13 | | |
| c12 | | |
| c11 | | Raghu Sastry, N. Ranganathan, Ramesh Jain: VLSI Architectures for Depth Estimation Using Intensity Gradient Analysis. IPPS 1993: 700-704 |
| c10 | | Mario Kovac, N. Ranganathan, M. Varanasi: SIGMA: A VLSI Chip for Galois Field GF(2m) Based Multiplication and Division. VLSI Design 1993: 25-30 |
| c9 | | Raghu Sastry, N. Ranganathan, Horst Bunke: Hardware Algorithms for Polygon Matching. VLSI Design 1993: 41-44 |
| 1992 | ||
| j5 | | Rajiv Mehrotra, Kameswara Rao Namuduri, Nagarajan Ranganathan: Gabor filter-based edge detection. Pattern Recognition 25(12): 1479-1494 (1992) |
| c8 | | Amar Mukherjee, Jeffrey W. Flieder, N. Ranganathan: MARVLE: A VLSI Chip for Variable Length Encoding and Decoding. ICCD 1992: 170-173 |
| c7 | | Mario Kovac, N. Ranganathan, M. Varanasi: A Systolic Algorithm and Architecture for Galois Field Arithmetic. IPPS 1992: 283-288 |
| 1991 | ||
| j4 | | N. Ranganathan, Sanjay Nichani, Rajiv Mehrotra: A VLSI architecture for a half-edge-based corner detector. Mach. Vis. Appl. 4(3): 165-181 (1991) |
| c6 | | Nagarajan Ranganathan, Rajiv Mehrotra, S. Subramaniam: A high speed systolic architecture for labeling connected components in an image. SPDP 1991: 818-825 |
| 1990 | ||
| j3 | | Rajiv Mehrotra, Sanjay Nichani, Nagarajan Ranganathan: Corner detection. Pattern Recognition 23(11): 1223-1233 (1990) |
| c5 | | N. Ranganathan, Hassan N. Srinidhi: Effect of Data Compression Hardware on the Performance of a Relational Database Machine. PARBASE 1990: 144-146 |
| c4 | | |
| 1989 | ||
| j2 | | Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan: Enhancing arithmetic and tree-based coding. Inf. Process. Manage. 25(3): 293-305 (1989) |
| c3 | | Mostafa A. Bassiouni, Amar Mukherjee, N. Ranganathan: On Software and Hardware Techniques of Data Engineering. ICDE 1989: 208-215 |
| 1988 | ||
| j1 | | N. Ranganathan, Mubarak Shah: A VLSI architecture for computing scale space. Computer Vision, Graphics, and Image Processing 43(2): 178-204 (1988) |
| c2 | | Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee: A scheme for data compression in supercomputers. SC 1988: 272-278 |
| c1 | | Mostafa A. Bassiouni, N. Ranganathan, Amar Mukherjee: Software and Hardware Enhancement of Arithmetic Coding. SSDBM 1988: 120-132 |
Colors in the list of coauthors
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