Mitchelle Rasquinha

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	2011
j1		Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay: A Scalable Design Methodology for Energy Minimization of STTRAM: A Circuit and Architecture Perspective. IEEE Trans. VLSI Syst. 19(5): 809-817 (2011)
c3		Syed Minhaj Hassan, Dhruv Choudhary, Mitchelle Rasquinha, Sudhakar Yalamanchili: Regulating Locality vs. Parallelism Tradeoffs in Multiple Memory Controller Environments. PACT 2011: 187-188
	2010
c2		Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatterjee, Saibal Mukhopadhyay, Sudhakar Yalamanchili: An energy efficient cache design using spin torque transfer (STT) RAM. ISLPED 2010: 389-394
	2009
c1		Subho Chatterjee, Mitchelle Rasquinha, Sudhakar Yalamanchili, Saibal Mukhopadhyay: A methodology for robust, energy efficient design of Spin-Torque-Transfer RAM arrays at scaled technologies. ICCAD 2009: 474-477

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