B. Ramakrishna Rau

Vinod Kathail, Shail Aditya, Robert Schreiber, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman: PICO: Automatically Designing Custom Computers. IEEE Computer 35(9): 39-47 (2002)

Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien: Constructing and exploiting linear schedules with prescribed parallelism. ACM Trans. Design Autom. Electr. Syst. 7(1): 159-172 (2002)

Robert Schreiber, Shail Aditya, Scott A. Mahlke, Vinod Kathail, B. Ramakrishna Rau, Darren C. Cronquist, Mukund Sivaraman: PICO-NPA: High-Level Synthesis of Nonprogrammable Hardware Accelerators. VLSI Signal Processing 31(2): 127-142 (2002)

B. Ramakrishna Rau, Michael S. Schlansker: Embedded Computer Architecture and Automation. IEEE Computer 34(4): 75-83 (2001)

Michael S. Schlansker, B. Ramakrishna Rau: EPIC: Explicititly Parallel Instruction Computing. IEEE Computer 33(2): 37-45 (2000)

Shail Aditya, Scott A. Mahlke, B. Ramakrishna Rau: Code size minimization and retargetable assembly for custom EPIC and VLIW instruction formats. ACM Trans. Design Autom. Electr. Syst. 5(4): 752-773 (2000)

Robert Schreiber, Shail Aditya, B. Ramakrishna Rau, Vinod Kathail, Scott A. Mahlke, Santosh G. Abraham, Greg Snider: High-Level Synthesis of Nonprogrammable Hardware Accelerators. ASAP 2000: 113-

Santosh G. Abraham, B. Ramakrishna Rau: Efficient design space exploration in PICO. CASES 2000: 71-79

B. Ramakrishna Rau: The era of embedded computing. CASES 2000: 119

B. Ramakrishna Rau, Michael S. Schlansker: Embedded Computing: New Directions in Architecture and Automation. HiPC 2000: 225-244

Alain Darte, Robert Schreiber, B. Ramakrishna Rau, Frédéric Vivien: A Constructive Solution to the Juggling Problem in Processor Array Synthesis. IPDPS 2000: 815-822

B. Ramakrishna Rau, Vinod Kathail, Shail Aditya: Machine-Description Driven Compilers for EPIC and VLIW Processors. Design Autom. for Emb. Sys. 4(2-3): 71-118 (1999)

Shail Aditya, B. Ramakrishna Rau, Vinod Kathail: Automatic Architectural Synthesis of VLIW and EPIC Processors. ISSS 1999: 107-113

John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau: Optimization of Machine Descriptions for Efficient Use. International Journal of Parallel Programming 26(4): 417-447 (1998)

Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau: Region-based compilation: Introduction, motivation, and initial experience. International Journal of Parallel Programming 25(2): 113-146 (1997)

B. Ramakrishna Rau: Iterative Modulo Scheduling. International Journal of Parallel Programming 24(1): 3-65 (1996)

Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker: Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. MICRO 1996: 58-67

John C. Gyllenhaal, Wen-mei W. Hwu, B. Ramakrishna Rau: Optimization of Machine Descriptions for Efficient Use. MICRO 1996: 349-358

Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau: Region-based compilation: an introduction and motivation. MICRO 1995: 158-168

B. Ramakrishna Rau: Iterative modulo scheduling: an algorithm for software pipelining loops. MICRO 1994: 63-74

Joseph A. Fisher, B. Ramakrishna Rau: Guest editors' introduction. The Journal of Supercomputing 7(1-2): 7 (1993)

B. Ramakrishna Rau, Joseph A. Fisher: Instruction-level parallel processing: History, overview, and perspective. The Journal of Supercomputing 7(1-2): 9-50 (1993)

Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker: Sentinel Scheduling for VLIW and Superscalar Processors. ACM Trans. Comput. Syst. 11(4): 376-408 (1993)

B. Ramakrishna Rau: Dynamically scheduled VLIW processors. MICRO 1993: 80-92

Santosh G. Abraham, Rabin A. Sugumar, Daniel Windheiser, B. Ramakrishna Rau, Rajiv Gupta: Predictability of load/store instruction latencies. MICRO 1993: 139-152

Nancy J. Warter, Scott A. Mahlke, Wen-mei W. Hwu, B. Ramakrishna Rau: Reverse If-Conversion. PLDI 1993: 290-299

Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker: Sentinel Scheduling for VLIW and Superscalar Processors. ASPLOS 1992: 238-247

B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai: Code generation schema for modulo scheduled loops. MICRO 1992: 158-169

B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker: Register Allocation for Software Pipelined Loops. PLDI 1992: 283-299

B. Ramakrishna Rau: Pseudo-Randomly Interleaved Memory. ISCA 1991: 74-83

B. Ramakrishna Rau: Data Flow and Dependence Analysis for Instruction Level Parallelism. LCPC 1991: 236-250

B. Ramakrishna Rau, David W. L. Yen, Wei C. Yen, Ross A. Towle: The Cydra 5 Departmental Supercomputer: Design Philosophies, Decisions, and Trade-offs. IEEE Computer 22(1): 12-35 (1989)

B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen: The Cydram 5 Stride-Insensitive Memory System. ICPP (1) 1989: 242-246

B. Ramakrishna Rau: Cydra 5 Directed Dataflow Architecture. COMPCON 1988: 106-113

Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker: Systematically derived instruction sets for high-level language support. ACM Southeast Regional Conference 1982: 73-84

B. Ramakrishna Rau, Christopher D. Glaeser, E. M. Greenawalt: Architectural Support for the Efficient Generation of Code for Horizontal Architectures. ASPLOS 1982: 96-99

B. Ramakrishna Rau, Christopher D. Glaeser, Raymond L. Picard: Efficient code generation for horizontal architectures: Compiler techniques and architectural support. ISCA 1982: 131-139

B. Ramakrishna Rau: Program Behavior and the Performance of Interleaved Memories. IEEE Trans. Computers 28(3): 191-199 (1979)

B. Ramakrishna Rau: Interleaved Memory Bandwidth in a Model of a Muyltiprocessor Computer System. IEEE Trans. Computers 28(9): 678-681 (1979)

B. Ramakrishna Rau, George E. Rossman: The Effect of Instruction Fetch Strategies upon the Performance of Pipelined Instruction Units. ISCA 1977: 80-89

B. Ramakrishna Rau: A new philosophy for interconnection on multilayer boards. DAC 1976: 225-231