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Rahul Razdan
2000 – 2009
- 2009
[c10]Eshel Haritan, Andreas Kuehlmann, Tina Jones, John Epperheimer, Jan M. Rabaey, Rahul Razdan, Naveen Gupta: EDA in flux: should I stay or should I go? DAC 2009: 91-92
[c9]
[c8]Rahul Razdan, Steve Esposito, Jay Lawrence, Peter Conner: Empirical results from the transformation of a large commercial technical computing environment. ESEM 2009: 248-256
1990 – 1999
- 1999
[c7]Rahul Razdan, Apurva Kalia, Manu Lauria: Verification of Systems-on-Chip Designs. VLSI Design 1999: 609- 1997
[c6]Gabriel P. Bischoff, Karl S. Brace, Samir Jain, Rahul Razdan: Formal Implementation Verification of the Bus Interface Unit for the Alpha 21264 Microprocessor. ICCD 1997: 16-24- 1994
[c5]Rahul Razdan, Karl S. Brace, Michael D. Smith: PRISC Software Acceleration Techniques. ICCD 1994: 145-149
[c4]Rahul Razdan, Michael D. Smith: A high-performance microarchitecture with hardware-programmable functional units. MICRO 1994: 172-180- 1993
[j2]Rahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich: Clock suppression techniques for synchronous circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1547-1556 (1993)- 1991
[c3]Joel Grodstein, Nick Rethman, Rahul Razdan, Gabriel P. Bischoff: Automatic Detection of MOS Synchronizers for Timing Verification. ICCAD 1991: 304-307- 1990
[c2]Rahul Razdan, Gabriel P. Bischoff, Ernst G. Ulrich: Exploitation of Periodicity in Logic Simulation of Synchronous Circuits. ICCAD 1990: 62-65
1980 – 1989
- 1989
[c1]Rahul Razdan, M. Anwaruddin, Predrag G. Kovijanic, R. Ganesh, H-C. Shih: An Interactive Sequential Test Pattern Generation System. ITC 1989: 38-46- 1986
[j1]Rahul Razdan, Andrzej J. Strojwas: A Statistical Design Rule Developer. IEEE Trans. on CAD of Integrated Circuits and Systems 5(4): 508-520 (1986)
Coauthor Index
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last updated on 2012-12-02 21:54 CET by the dblp team



