| 2012 | ||
|---|---|---|
| c24 | Xinli Gu, Jeff Rearick, Bill Eklow, Martin Keim, Jun Qian, Artur Jutman, Krishnendu Chakrabarty, Erik Larsson: Re-using chip level DFT at board level. European Test Symposium 2012: 1 | |
| 2011 | ||
| c23 | Baosheng Wang, Jayalakshmi Rajaraman, Kanwaldeep Sobti, Derrick Losli, Jeff Rearick: Structural tests of slave clock gating in low-power flip-flop. VTS 2011: 254-259 | |
| 2010 | ||
| c22 | Vance Threatt, Atchyuth Gorti, Jeff Rearick, Shaishav Parikh, Anirudh Kadiyala, Aditya Jagirdar, Andy Halliday: Vendor-agnostic native compression engine. ITC 2010: 819 | |
| c21 | Janine Chen, Jing Zeng, Li-C. Wang, Jeff Rearick, Michael Mateja: Selecting the most relevant structural Fmax for system Fmax correlation. VTS 2010: 99-104 | |
| 2009 | ||
| j3 | Ozgur Sinanoglu, Erik Jan Marinissen, Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick: Test Data Volume Comparison: Monolithic vs. Modular SoC Testing. IEEE Design & Test of Computers 26(3): 25-37 (2009) | |
| c20 | S. Gurumurthy, D. Bertanzetti, P. Jakobsen, Jeff Rearick: Cache-resident self-testing for I/O circuitry. ITC 2009: 1-8 | |
| c19 | ||
| 2008 | ||
| j2 | Bart Vermeulen, Neal Stollon, Rolf Kühnis, Gary Swoboda, Jeff Rearick: Overview of Debug Standardization Activities. IEEE Design & Test of Computers 25(3): 258-267 (2008) | |
| c18 | Jeff Rearick: This is a Test: How to Tell if DFT and Test Are Adding Value to Your Company. ITC 2008 | |
| 2007 | ||
| j1 | Donghwi Lee, Erik H. Volkerink, Intaik Park, Jeff Rearick: Empirical Validation of Yield Recovery Using Idle-Cycle Insertion. IEEE Design & Test of Computers 24(4): 362-372 (2007) | |
| c17 | Anuja Sehgal, Jeff Fitzgerald, Jeff Rearick: Test cost reduction for the AMD™ Athlon processor using test partitioning. ITC 2007: 1-10 | |
| 2006 | ||
| c16 | Ken Posse, Al Crouch, Jeff Rearick, Bill Eklow, Mike Laisne, Ben Bennetts, Jason Doege, Mike Ricchetti, J.-F. Cote: IEEE P1687: Toward Standardized Access of Embedded Instrumentation. ITC 2006: 1-8 | |
| c15 | ||
| c14 | Jeff Rearick, Aaron Volz: A Case Study of Using IEEE P1687 (IJTAG) for High-Speed Serial I/O Characterization and Testing. ITC 2006: 1-8 | |
| 2005 | ||
| c13 | Jeff Rearick, Bill Eklow, Ken Posse, Al Crouch, Ben Bennetts: IJTAG (internal JTAG): a step toward a DFT standard. ITC 2005: 8 | |
| c12 | ||
| 2004 | ||
| c11 | Jeff Rearick, Sylvia Patterson, Krista Dorner: Integrating Boundary Scan into Multi-GHz I/O Circuitry. ITC 2004: 560-566 | |
| 2003 | ||
| c10 | Suzette Vandivier, Mark Wahl, Jeff Rearick: First IC Validation of IEEE Std. 1149.6. ITC 2003: 632-639 | |
| c9 | Manish Sharma, Janak H. Patel, Jeff Rearick: Test Data Compression and Test Time Reduction of Longest-Path-Per-Gate Tests based on Illinois Scan Architecture. VTS 2003: 15-21 | |
| 2001 | ||
| c8 | Young Kim, Benny Lai, Kenneth P. Parker, Jeff Rearick: Frequency detection-based boundary-scan testing of AC coupled nets. ITC 2001: 46-53 | |
| c7 | ||
| 2000 | ||
| c6 | Peter C. Maxwell, Jeff Rearick: Deception by design: fooling ourselves with gate-level models. ITC 2000: 921-929 | |
| 1999 | ||
| c5 | ||
| 1998 | ||
| c4 | Peter C. Maxwell, Jeff Rearick: Estimation of defect-free IDDQ in submicron circuits using switch level simulation. ITC 1998: 882-889 | |
| 1997 | ||
| c3 | ||
| c2 | ||
| 1993 | ||
| c1 | ||
Colors in the list of coauthors
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