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 | 2013 | |
|---|---|---|
| j20 |      | M. Victoria Bueno-Delgado, Renato Ferrero, Filippo Gandino, Pablo Pavón-Mariño, Maurizio Rebaudengo: A Geometric Distribution Reader Anti-Collision Protocol for RFID Dense Reader Environments. IEEE T. Automation Science and Engineering 10(2): 296-306 (2013) |
| j19 | | Filippo Gandino, Renato Ferrero, Bartolomeo Montrucchio, Maurizio Rebaudengo: DCNS: An Adaptable High Throughput RFID Reader-to-Reader Anticollision Protocol. IEEE Trans. Parallel Distrib. Syst. 24(5): 893-905 (2013) |
| 2012 | ||
| j18 | | Renato Ferrero, Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo: A Fair and High Throughput Reader-to-Reader Anticollision Protocol in Dense RFID Networks. IEEE Trans. Industrial Informatics 8(3): 697-706 (2012) |
| c84 | | Linchao Zhang, Renato Ferrero, Filippo Gandino, Maurizio Rebaudengo: A Comparison between Single and Additive Contribution in RFID Reader-to-Reader Interference Models. IMIS 2012: 177-184 |
| 2011 | ||
| j17 | | Filippo Gandino, Renato Ferrero, Bartolomeo Montrucchio, Maurizio Rebaudengo: Probabilistic DCS: An RFID reader-to-reader anti-collision protocol. J. Network and Computer Applications 34(3): 821-832 (2011) |
| c83 | | Linchao Zhang, Erwing Ricardo Sanchez, Maurizio Rebaudengo: Evaluation Framework of Opportunistic Flooding in Wireless Sensor Networks. EUC 2011: 87-94 |
| c82 | | Linchao Zhang, Erwing Ricardo Sanchez, Maurizio Rebaudengo: Performance evaluation of reliable and unreliable opportunistic flooding in wireless sensor network. ICON 2011: 7-12 |
| c81 | | Erwing Ricardo Sanchez, Laura M. Murillo, Bartolomeo Montrucchio, Maurizio Rebaudengo: An Adaptive Power-Aware Multi-hop Routing Algorithm for Wireless Sensor Networks. ITNG 2011: 112-116 |
| c80 | | Erwing Ricardo Sanchez, Bartolomeo Montrucchio, Laura M. Murillo, Maurizio Rebaudengo: Adaptive Fuzzy-MAC for Power Reduction in Wireless Sensor Networks. NTMS 2011: 1-5 |
| c79 |  | Erwing Ricardo Sanchez, Bartolomeo Montrucchio, Maurizio Rebaudengo: Monitoring and Modeling Building Energy Expenditure with Sensor Networks. PECCS 2011: 283-287 |
| 2010 | ||
| j16 | | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda: Exploiting an infrastructure-intellectual property for systems-on-chip test, diagnosis and silicon debug. IET Computers & Digital Techniques 4(2): 104-113 (2010) |
| j15 | | Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo: Tampering in RFID: A Survey on Risks and Defenses. MONET 15(4): 502-516 (2010) |
| 2009 | ||
| j14 | | Filippo Gandino, Erwing Ricardo Sanchez, Bartolomeo Montrucchio, Maurizio Rebaudengo: Opportunities and Constraints for Wide Adoption of RFID in Agri-Food. IJAPUC 1(2): 49-67 (2009) |
| j13 | | Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo, Erwing Ricardo Sanchez: On Improving Automation by Integrating RFID in the Traceability Management of the Agri-Food Sector. IEEE Transactions on Industrial Electronics 56(7): 2357-2365 (2009) |
| c78 | | Filippo Gandino, Renato Ferrero, Bartolomeo Montrucchio, Maurizio Rebaudengo: Introducing Probability in RFID Reader-to-Reader Anti-collision. NCA 2009: 250-257 |
| 2007 | ||
| j12 | | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda: A System-layer Infrastructure for SoC Diagnosis. J. Electronic Testing 23(5): 389-404 (2007) |
| c77 | | Paolo Bernardi, Claudio Demartini, Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo, Erwing Ricardo Sanchez: Agri-Food Traceability Management using a RFID System with Privacy Protection. AINA 2007: 68-75 |
| c76 | | Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda: Safety Evaluation of NanoFabrics. DFT 2007: 418-426 |
| c75 | | Paolo Bernardi, Filippo Gandino, Bartolomeo Montrucchio, Maurizio Rebaudengo, Erwing Ricardo Sanchez: Design of an UHF RFID transponder for secure authentication. ACM Great Lakes Symposium on VLSI 2007: 387-392 |
| 2006 | ||
| b1 | | Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Software-Implemented Hardware Fault Tolerance. Springer 2006, isbn 978-0-387-26060-0, pp. I-XI, 1-224 |
| j11 | | Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: A New Hybrid Fault Detection Technique for Systems-on-a-Chip. IEEE Trans. Computers 55(2): 185-198 (2006) |
| c74 | | Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto: Combined software and hardware techniques for the design of reliable IP processors. DFT 2006: 265-273 |
| c73 | | Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda: Embedded Memory Diagnosis: An Industrial Workflow. ITC 2006: 1-9 |
| c72 | | Davide Appello, Vincenzo Tancorre, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda: On the Automation of the Test Flow of Complex SoCs. VTS 2006: 166-171 |
| c71 | | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda: A Pattern Ordering Algorithm for Reducing the Size of Fault Dictionaries. VTS 2006: 386-391 |
| 2005 | ||
| c70 | | Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Integrated Approach for Increasing the Soft-Error Detection Capabilities in SoCs processors. DFT 2005: 445-453 |
| c69 | | Paolo Bernardi, Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: On-Line Detection of Control-Flow Errors in SoCs by Means of an Infrastructure IP Core. DSN 2005: 50-58 |
| c68 | | Alberto Manzone, Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Ernesto Sánchez, Matteo Sonza Reorda: Integrating BIST Techniques for On-Line SoC Testing. IOLTS 2005: 235-240 |
| c67 | | Paolo Bernardi, Michelangelo Grosso, Maurizio Rebaudengo, Matteo Sonza Reorda: Exploiting an I-IP for both Test and Silicon Debug of Microprocessor Cores. MTV 2005: 55-62 |
| 2004 | ||
| j10 | | Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Paolo Bernardi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda: A BIST-based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. J. Electronic Testing 20(1): 79-87 (2004) |
| j9 | | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A New Approach to Software-Implemented Fault Tolerance. J. Electronic Testing 20(4): 433-437 (2004) |
| c66 | | M. Bellato, Paolo Bernardi, D. Bortolato, A. Candelori, M. Ceschia, Alessandro Paccagnella, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, P. Zambolin: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA. DATE 2004: 584-589 |
| c65 | | Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda: Exploiting an I-IP for In-Field SOC Test. DFT 2004: 404-412 |
| c64 | | Leticia Maria Veiras Bolzani, Maurizio Rebaudengo, Matteo Sonza Reorda, Fabian Vargas, Massimo Violante: Hybrid Soft Error Detection by Means of Infrastructure IP Cores. IOLTS 2004: 79-88 |
| c63 | | Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda: Using Infrastructure IPs to Support SW-Based Self-Test of Processor Cores. MTV 2004: 22-27 |
| 2003 | ||
| j8 | | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Accurate Analysis of Single Event Upsets in a Pipelined Microprocessor. J. Electronic Testing 19(5): 577-584 (2003) |
| j7 | | Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: New techniques for efficiently assessing reliability of SOCs. Microelectronics Journal 34(1): 53-61 (2003) |
| c62 | | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An Accurate Analysis of the Effects of Soft Errors in the Instruction and Data Caches of a Pipelined Microprocessor. DATE 2003: 10602-10607 |
| c61 | | Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A P1500-Compatible Programmable BIST Approach for the Test of Embedded Flash Memories. DATE 2003: 10720-10725 |
| c60 | | Olga Goloubeva, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Soft-Error Detection Using Control Flow Assertions. DFT 2003: 581-588 |
| c59 | | Paolo Bernardi, Maurizio Rebaudengo, Matteo Sonza Reorda: An efficient algorithm for the extraction of compressed diagnostic information from embedded memory cores. ETFA (1) 2003: 417-421 |
| c58 | | Massimo Violante, M. Ceschia, Matteo Sonza Reorda, Alessandro Paccagnella, Paolo Bernardi, Maurizio Rebaudengo, D. Bortolato, M. Bellato, P. Zambolin, A. Candelori: Analyzing SEU Effects in SRAM-based FPGAs. IOLTS 2003: 119-123 |
| c57 | | Davide Appello, Paolo Bernardi, Alessandra Fudoli, Maurizio Rebaudengo, Matteo Sonza Reorda, Vincenzo Tancorre, Massimo Violante: Exploiting Programmable BIST For The Diagnosis of Embedded Memory Cores. ITC 2003: 379-385 |
| 2002 | ||
| j6 | | Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: An FPGA-Based Approach for Speeding-Up Fault Injection Campaigns on Safety-Critical Circuits. J. Electronic Testing 18(3): 261-271 (2002) |
| j5 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero: Initializability analysis of synchronous sequential circuits. ACM Trans. Design Autom. Electr. Syst. 7(2): 249-264 (2002) |
| c56 | | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: A New Functional Fault Model for FPGA Application-Oriented Testing. DFT 2002: 372-380 |
| c55 | | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Simulation-Based Analysis of SEU Effects on SRAM-based FPGAs. FPL 2002: 607-615 |
| c54 | | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Analysis of SEU Effects in a Pipelined Processor. IOLTW 2002: 112-116 |
| c53 | | Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda: A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. IOLTW 2002: 206-210 |
| c52 | | Davide Appello, Alessandra Fudoli, Vincenzo Tancorre, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda: A BIST-Based Solution for the Diagnosis of Embedded Memories Adopting Image Processing Techniques. MTDT 2002: 12-16 |
| 2001 | ||
| c51 | | Davide Appello, Fulvio Corno, M. Giovinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: A P1500 Compliant BIST-Based Approach to Embedded RAM Diagnosis. Asian Test Symposium 2001: 97-102 |
| c50 | | Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection for Microprocessor Systems. Asian Test Symposium 2001: 304- |
| c49 | | Ph. Cheynet, B. Nicolescu, Raoul Velazco, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: System safety through automatic high-level code transformations: an experimental evaluation. DATE 2001: 297-301 |
| c48 | | Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA-Based Techniques for Fault Injection Campaigns on VLSI Circuits . DFT 2001: 250-258 |
| c47 | | Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. FPL 2001: 493-502 |
| c46 | | Pierluigi Civera, Luca Macchiarulo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting FPGA for Accelerating Fault Injection Experiments. IOLTW 2001: 9-13 |
| c45 | | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Marco Torchiano: A Source-to-Source Compiler for Generating Dependable Software. SCAM 2001: 35-44 |
| 2000 | ||
| c44 | | Marcello Lajolo, Luciano Lavagno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Automatic test bench generation for simulation-based validation. CODES 2000: 136-140 |
| c43 | | Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno: Evaluating System Dependability in a Co-Design Framework. DATE 2000: 586-590 |
| c42 | | Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante: An Experimental Evaluation of the Effectiveness of Automatic Rule-Based Transformations for Safety-Critical Applications. DFT 2000: 257-265 |
| c41 | | Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Prediction of Power Requirements for High-Speed Circuits. EvoWorkshops 2000: 247-254 |
| c40 | | Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno: Behavioral-level test vector generation for system-on-chip designs. HLDVT 2000: 21-26 |
| c39 | | Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Ph. Cheynet, B. Nicolescu, Raoul Velazco: Evaluating the Effectiveness of a Software Fault-Tolerance Technique on RISC- and CISC-Based Architectures. IOLTW 2000: 17- |
| c38 | | B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: New Techniques for Accelerating Fault Injection in VHDL Descriptions. IOLTW 2000: 61-66 |
| c37 | | B. Parrotta, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Speeding-Up Fault Injection Campaigns in VHDL Models. SAFECOMP 2000: 27-36 |
| c36 | | Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero, Massimo Violante: Low Power BIST via Non-Linear Hybrid Cellular Automata. VTS 2000: 29-34 |
| 1999 | ||
| j4 | | Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda: Fault Injection for Embedded Microprocessor-based Systems. J. UCS 5(10): 693-711 (1999) |
| c35 | | Maurizio Rebaudengo, Matteo Sonza Reorda, Marco Torchiano, Massimo Violante: Soft-Error Detection through Software Fault-Tolerance Techniques. DFT 1999: 210-218 |
| c34 | | Fulvio Corno, Matteo Sonza Reorda, Maurizio Rebaudengo, Massimo Violante: Optimal Vector Selection for Low Power BIST. DFT 1999: 219-226 |
| c33 | | Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Test Pattern Generation Under Low Power Constraints. EvoWorkshops 1999: 162-170 |
| c32 | | Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: ALPS: A Peak Power Estimation Tool for Sequential Circuits. Great Lakes Symposium on VLSI 1999: 350-353 |
| c31 | | Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda: FlexFi: A Flexible Fault Injection Environment for Microprocessor-Based Systems. SAFECOMP 1999: 323-335 |
| c30 | | Maurizio Rebaudengo, Matteo Sonza Reorda: Evaluating the Fault Tolerance Capabilities of Embedded Systems via BDM . VTS 1999: 452-459 |
| 1998 | ||
| j3 | | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: EXFI: a low-cost fault injection system for embedded microprocessor-based boards. ACM Trans. Design Autom. Electr. Syst. 3(4): 626-634 (1998) |
| c29 | | Alfredo Benso, Maurizio Rebaudengo, Matteo Sonza Reorda, Pierluigi Civera: An Integrated HW and SW Fault Injection Environment for Real-Time Systems. DFT 1998: 117- |
| c28 | | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: A fault injection environment for microprocessor-based boards. ITC 1998: 768-773 |
| c27 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: A Test Pattern Generation Methodology for Low-Power Consumption. VTS 1998: 453-459 |
| 1997 | ||
| c26 | | Silvia Chiusano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Guaranteeing Testability in Re-encoding for Low Power. Asian Test Symposium 1997: 30-35 |
| c25 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero: A Genetic Algorithm for the Computation of Initialization Sequences for Synchronous Sequential Circuits. Asian Test Symposium 1997: 56-61 |
| c24 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante: Exploiting Logic Simulation to Improve Simulation-based Sequential ATPG. Asian Test Symposium 1997: 68-73 |
| c23 | | Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Paolo Prinetto, Matteo Sonza Reorda, Giovanni Squillero: Simulation-based verification of network protocols performance. CHARME 1997: 236-251 |
| c22 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: New static compaction techniques of test sequences for sequential circuits. ED&TC 1997: 37-43 |
| c21 | | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Raimund Ubar: A new approach to build a low-level malicious fault list starting from high-level description and alternative graphs. ED&TC 1997: 560-565 |
| c20 | | Alfredo Benso, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Jaan Raik, Raimund Ubar: Exploiting High-Level Descriptions for Circuits Fault Tolerance Assessments. DFT 1997: 212-217 |
| c19 | | F. Bianchi, Fulvio Corno, Maurizio Rebaudengo, Matteo Sonza Reorda, Roberto Ansaloni: Boolean Function Manipulation on a Parallel System Using BDDs. HPCN Europe 1997: 916-928 |
| c18 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Giovanni Squillero: A new Approach for Initialization Sequences Computation for Synchronous Sequential Circuits. ICCD 1997: 381-386 |
| c17 | | Mario Baldi, Fulvio Corno, Maurizio Rebaudengo, Giovanni Squillero: GA-Based Performance Analysis of Network Protocols. ICTAI 1997: 118-124 |
| c16 | | S. Chuisano, Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Exploiting Symbolic Techniques within Genetic Algorithms for Power Optimization. ICTAI 1997: 133- |
| c15 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: SAARA: a simulated annealing algorithm for test pattern generation for digital circuits. SAC 1997: 228-232 |
| 1996 | ||
| j2 | | Maurizio Rebaudengo, Matteo Sonza Reorda: GALLO: a genetic algorithm for floorplan area optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 943-951 (1996) |
| j1 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: GATTO: a genetic algorithm for automatic test pattern generation for large synchronous sequential circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 15(8): 991-1000 (1996) |
| c14 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Maurizio Damiani, Leonardo Impagliazzo, G. Sartore: On-line Testing of an Off-the-shelf Microprocessor Board for Safety-critical Applications. EDCC 1996: 190-202 |
| c13 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: A Parallel Genetic Algorithm for Automatic Generation of Test Sequences for Digital Circuits. HPCN Europe 1996: 454-459 |
| c12 | | Gavril Godza, Maurizio Rebaudengo, Matteo Sonza Reorda: Using Parallel Genetic Algorithms for Solving the Min-Cut Problem. HPCN Europe 1996: 985-986 |
| c11 | | Maurizio Rebaudengo, Matteo Sonza Reorda: A Cellular Genetic Algorithm for the Floorplan Area Optimization Problem on a SIMD Architecture. HPCN Europe 1996: 987-988 |
| c10 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Comparing Topological, Symbolic and GA-based ATPGs: An Experimental Approach. ITC 1996: 39-47 |
| c9 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Partial Scan Flip Flop Selection for Simulation-Based Sequential ATPGs. ITC 1996: 558-564 |
| c8 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: Exploiting Competing Subpopulations for Automatic Generation of Test Sequences for Digital Cicuits. PPSN 1996: 792-800 |
| 1995 | ||
| c7 | | P. P. Delsanto, S. Biancotto, M. Scalerandi, Maurizio Rebaudengo, Matteo Sonza Reorda: Exploiting massively parallel architectures for the solution of diffusion and propagation problems. HPCN Europe 1995: 1-6 |
| c6 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva: A PVM tool for automatic test generation on parallel and distributed systems. HPCN Europe 1995: 39-44 |
| c5 | | Silvano Gai, Maurizio Rebaudengo, Matteo Sonza Reorda: An improved data parallel algorithm for Boolean function manipulation using BDDs. PDP 1995: 33-41 |
| c4 | | Fulvio Corno, Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva: A portable ATPG tool for parallel and distributed systems. VTS 1995: 29-34 |
| 1994 | ||
| c3 | | Matteo Sonza Reorda, Maurizio Rebaudengo: A Genetic Algorithm for Floorplan Area Optimization. International Conference on Evolutionary Computation 1994: 93-96 |
| c2 | | Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda, Enzo Veiluva: GATTO: An Intelligent Tool for Automatic Test Pattern Generation for Digital Circuits. ICTAI 1994: 411-417 |
| c1 | | Paolo Prinetto, Maurizio Rebaudengo, Matteo Sonza Reorda: An Automatic Test Pattern Generator for Large Sequential Circuits Based on Genetic Algorithms. ITC 1994: 240-249 |
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