Sherief Reda

Sherief Reda, Abdullah Nazma Nowroz, Ryan Cochran, Stefan Angelevski: Post-silicon power mapping techniques for integrated circuits. Integration 46(1): 69-79 (2013)

Kangqiao Hu, Abdullah Nazma Nowroz, Sherief Reda, Farinaz Koushanfar: High-sensitivity hardware trojan detection using multimodal characterization. DATE 2013: 1271-1276

Francesco Paterna, Sherief Reda: Mitigating dark-silicon problems using superlattice-based thermoelectric coolers. DATE 2013: 1391-1394

Sherief Reda, Abdullah Nazma Nowroz: Power Modeling and Characterization of Computing Devices: A Survey. Foundations and Trends in Electronic Design Automation 6(2): 121-216 (2012)

Sherief Reda, Ryan Cochran, Ayse Kivilcim Coskun: Adaptive Power Capping for Servers with Multithreaded Workloads. IEEE Micro 32(5): 64-75 (2012)

Ryan Cochran, Sherief Reda: Thermal prediction and adaptive control through workload phase detection. ACM Trans. Design Autom. Electr. Syst. 18(1): 7 (2012)

Kumud Nepal, Onur Ulusel, R. Iris Bahar, Sherief Reda: Fast Multi-Objective Algorithmic Design Co-Exploration for FPGA-based Accelerators. FCCM 2012: 65-68

Dhireesha Kudithipudi, Ayse Kivilcim Coskun, Sherief Reda, Qinru Qiu: Temperature-aware computing: Achievements and remaining challenges. IGCC 2012: 1-3

Sherief Reda: Thermal and Power Characterization of Real Computing Devices. IEEE J. Emerg. Sel. Topics Circuits Syst. 1(2): 76-87 (2011)

Sherief Reda, Ryan Cochran, Abdullah Nazma Nowroz: Improved Thermal Tracking for Processors Using Hard and Soft Sensor Allocation Techniques. IEEE Trans. Computers 60(6): 841-851 (2011)

Abdullah Nazma Nowroz, Gary Woods, Sherief Reda: Improved post-silicon power modeling using AC lock-in techniques. DAC 2011: 101-106

Abdullah Nazma Nowroz, Sherief Reda: Thermal and power characterization of field-programmable gate arrays. FPGA 2011: 111-114

Ryan Cochran, Can Hankendi, Ayse Kivilcim Coskun, Sherief Reda: Identifying the optimal energy-efficient operating points of parallel workloads. ICCAD 2011: 608-615

Ryan Cochran, Can Hankendi, Ayse Kivilcim Coskun, Sherief Reda: Pack & Cap: adaptive DVFS and thread packing under power caps. MICRO 2011: 175-185

Nauman H. Khan, Sherief Reda, Soha Hassoun: Early estimation of TSV area for power delivery in 3-D integrated circuits. 3DIC 2010: 1-6

Abdullah Nazma Nowroz, Ryan Cochran, Sherief Reda: Thermal monitoring of real processors: techniques for sensor allocation and full characterization. DAC 2010: 56-61

Ryan Cochran, Sherief Reda: Consistent runtime thermal prediction and control through workload phase detection. DAC 2010: 62-67

Ryan Cochran, Abdullah Nazma Nowroz, Sherief Reda: Post-silicon power characterization using thermal infrared emissions. ISLPED 2010: 331-336

Jinhai Qiu, Sherief Reda, Soha Hassoun: Fast, accurate a priori routing delay estimation. SLIP 2010: 77-82

Sherief Reda, Janet Meiling Wang (Eds.): International Workshop on System Level Interconnect Prediction Workshop, SLIP 2010, Anaheim, CA, USA, June 13, 2010. ACM 2010, isbn 978-1-4503-0037-7

Sherief Reda, Gregory Smith, Larry Smith: Maximizing the Functional Yield of Wafer-to-Wafer 3-D Integration. IEEE Trans. VLSI Syst. 17(9): 1357-1362 (2009)

Ryan Cochran, Sherief Reda: Spectral techniques for high-resolution thermal characterization with limited sensor data. DAC 2009: 478-483

Sherief Reda, Sani R. Nassif: Analyzing the impact of process variations on parametric measurements: Novel models and applications. DATE 2009: 375-380

Roto Le, Sherief Reda, R. Iris Bahar: High-performance, cost-effective heterogeneous 3D FPGA architectures. FPGA 2009: 286

Michael Kadin, Sherief Reda, Augustus K. Uht: Central vs. distributed dynamic thermal management for multi-core processors: which one is better? ACM Great Lakes Symposium on VLSI 2009: 137-140

Roto Le, Sherief Reda, R. Iris Bahar: High-performance, cost-effective heterogeneous 3D FPGA architectures. ACM Great Lakes Symposium on VLSI 2009: 251-256

Sherief Reda, Aung Si, R. Iris Bahar: Reducing the leakage and timing variability of 2D ICcs using 3D ICs. ISLPED 2009: 283-286

Sherief Reda: Using circuit structural analysis techniques for networks in systems biology. SLIP 2009: 37-44

Chung-Kuan Cheng, Sherief Reda (Eds.): The 11th International Workshop on System-Level Interconnect Prediction (SLIP 2009), San Francisco, CA, USA, July 26-27, 2009, Proceedings. ACM 2009, isbn 978-1-60558-576-5

Cesare Ferri, Sherief Reda, R. Iris Bahar: Parametric yield management for 3D ICs: Models and strategies for improvement. JETC 4(4) (2008)

Brendan Hargreaves, Henrik Hult, Sherief Reda: Within-die process variations: How accurately can they be statistically modeled? ASP-DAC 2008: 524-530

Michael Kadin, Sherief Reda: Frequency and voltage planning for multi-core processors under thermal constraints. ICCD 2008: 463-470

Michael Kadin, Sherief Reda: Frequency planning for multi-core processors under thermal constraints. ISLPED 2008: 213-216

Cesare Ferri, Sherief Reda, R. Iris Bahar: Strategies for improving the parametric yield and profits of 3D ICs. ICCAD 2007: 220-226

David Meisner, Sherief Reda: Hardware libraries: An architecture for economic acceleration in soft multi-core environments. ICCD 2007: 179-186

Andrew B. Kahng, Sherief Reda, Puneet Sharma: On-Line Adjustable Buffering for Runtime Power Reduction. ISQED 2007: 550-555

Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky: Computer-Aided Optimization of DNA Array Design and Manufacturing. IEEE Trans. on CAD of Integrated Circuits and Systems 25(2): 305-320 (2006)

Andrew B. Kahng, Sherief Reda: New and improved BIST diagnosis methods from combinatorial Group testing theory. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 533-543 (2006)

Gi-Joon Nam, Sherief Reda, Charles J. Alpert, Paul Villarrubia, Andrew B. Kahng: A Fast Hierarchical Quadratic Placement Algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 678-691 (2006)

Andrew B. Kahng, Sherief Reda: Wirelength minimization for min-cut placements via placement feedback. IEEE Trans. on CAD of Integrated Circuits and Systems 25(7): 1301-1312 (2006)

Andrew B. Kahng, Sherief Reda: Zero-Change Netlist Transformations: A New Technique for Placement Benchmarking. IEEE Trans. on CAD of Integrated Circuits and Systems 25(12): 2806-2819 (2006)

Sherief Reda, Amit Chowdhary: Effective linear programming based placement methods. ISPD 2006: 186-191

Andrew B. Kahng, Sherief Reda: A tale of two nets: studies of wirelength progression in physical design. SLIP 2006: 17-24

Yongseok Cheon, Pei-Hsin Ho, Andrew B. Kahng, Sherief Reda, Qinke Wang: Power-aware placement. DAC 2005: 795-800

Andrew B. Kahng, Sherief Reda: Intrinsic shortest path length: a new, accurate a priori wirelength estimator. ICCAD 2005: 173-180

Andrew B. Kahng, Sherief Reda, Qinke Wang: Architecture and details of a high quality, large-scale analytical placer. ICCAD 2005: 891-898

Charles J. Alpert, Andrew B. Kahng, Gi-Joon Nam, Sherief Reda, Paul Villarrubia: A semi-persistent clustering technique for VLSI circuit placement. ISPD 2005: 200-207

Andrew B. Kahng, Sherief Reda: Evaluation of placer suboptimality via zero-change netlist transformations. ISPD 2005: 208-215

Andrew B. Kahng, Sherief Reda, Qinke Wang: APlace: a general analytic placement framework. ISPD 2005: 233-235

Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky: Scalable Heuristics for Design of DNA Probe Arrays. Journal of Computational Biology 11(2/3): 429-447 (2004)

Andrew B. Kahng, Sherief Reda: Match twice and stitch: a new TSP tour construction heuristic. Oper. Res. Lett. 32(6): 499-509 (2004)

Andrew B. Kahng, Sherief Reda: Combinatorial group testing methods for the BIST diagnosis problem. ASP-DAC 2004: 113-116

Andrew B. Kahng, Sherief Reda: Placement feedback: a concept and method for better min-cut placements. DAC 2004: 357-362

Andrew B. Kahng, Igor L. Markov, Sherief Reda: Boosting: Min-Cut Placement with Improved Signal Delay. DATE 2004: 1098-1103

Andrew B. Kahng, Igor L. Markov, Sherief Reda: On legalization of row-based placements. ACM Great Lakes Symposium on VLSI 2004: 214-219

Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky: Evaluation of Placement Techniques for DNA Probe Array Layout. ICCAD 2003: 262-269

Andrew B. Kahng, Ion I. Mandoiu, Sherief Reda, Xu Xu, Alexander Zelikovsky: Design Flow Enhancements for DNA Arrays. ICCD 2003: 116-

Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky: Engineering a scalable placement heuristic for DNA probe arrays. RECOMB 2003: 148-156

Sherief Reda, Alex Orailoglu: Reducing Test Application Time Through Test Data Mutation Encoding. DATE 2002: 387-393

Sherief Reda, Rolf Drechsler, Alex Orailoglu: On the Relation between SAT and BDDs for Equivalence Checking. ISQED 2002: 394-399

Andrew B. Kahng, Ion I. Mandoiu, Pavel A. Pevzner, Sherief Reda, Alexander Zelikovsky: Border Length Minimization in DNA Array Design. WABI 2002: 435-448

Sherief Reda, A. Salem: Combinational equivalence checking using Boolean satisfiability and binary decision diagrams. DATE 2001: 122-126