Jihong Ren

Kambiz Kaviani, Masum Hossain, Meisam Honarvar Nazari, Fred Heaton, Jihong Ren, Jared Zerbe: A 27-Gb/s, 0.41-mW/Gb/s 1-tap predictive decision feedback equalizer in 40-nm low-power CMOS. CICC 2012: 1-4

Jared Zerbe, Barry Daly, Lei Luo, Bill Stonecypher, Wayne D. Dettloff, John C. Eble, Teva Stone, Jihong Ren, Brian S. Leibowitz, Michael Bucher, Patrick Satarzadeh, Qi Lin, Yue Lu, Ravi Kollipara: A 5 Gb/s Link With Matched Source Synchronous and Common-Mode Clocking Techniques. J. Solid-State Circuits 46(4): 974-985 (2011)

Jaeha Kim, E.-Hung Chen, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Jared Zerbe, Chih-Kong Ken Yang: Equalizer Design and Performance Trade-Offs in ADC-Based Serial Links. IEEE Trans. on Circuits and Systems 58-I(9): 2096-2107 (2011)

Jaeha Kim, Jihong Ren, Brian S. Leibowitz, Patrick Satarzadeh, Ali-Azam Abbasfar, Jared Zerbe: Equalizer design and performance trade-offs in ADC-based serial links. CICC 2010: 1-8

Jaeha Kim, Brian S. Leibowitz, Jihong Ren, Chris J. Madden: Simulation and Analysis of Random Decision Errors in Clocked Comparators. IEEE Trans. on Circuits and Systems 56-I(8): 1844-1857 (2009)

Jaeha Kim, Jihong Ren, Mark A. Horowitz: Stochastic steady-state and AC analyses of mixed-signal systems. DAC 2009: 376-381

Suwen Yang, Mark R. Greenstreet, Jihong Ren: A Jitter Attenuating Timing Chain. ASYNC 2007: 25-38

Mark R. Greenstreet, Jihong Ren: Surfing Interconnect. ASYNC 2006: 98-106

Jihong Ren, Mark R. Greenstreet: A unified optimization framework for equalization filter synthesis. DAC 2005: 638-643

Jihong Ren, Mark R. Greenstreet: A Signal Integrity Test Bed for PCB Buses. ICCD 2004: 132-137

Jihong Ren, Mark R. Greenstreet: Crosstalk Cancellation for Realistic PCB Buses. PATMOS 2004: 48-57

Jihong Ren, Mark R. Greenstreet: Synthesizing optimal filters for crosstalk-cancellation for high-speed buses. DAC 2003: 592-597

Jihong Ren, Mark R. Greenstreet: Equalizing Filter Design for Crosstalk Cancellation. ISVLSI 2003: 272-274