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 | 2012 | |
|---|---|---|
| c74 |      | Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Vincent Kerzerho, Olivier Potin, Michel Renovell: Making predictive analog/RF alternate test strategy independent of training set size. ITC 2012: 1-9 |
| c73 | | Haithem Ayari, Florence Azaïs, Serge Bernard, Mariane Comte, Michel Renovell, Vincent Kerzerho, Olivier Potin, Christophe Kelma: Smart selection of indirect parameters for DC-based alternate RF IC testing. VTS 2012: 19-24 |
| 2011 | ||
| j43 | | Vincent Kerzerho, Mariane Comte, Florence Azaïs, Philippe Cauvet, Serge Bernard, Michel Renovell: Digital Test Method for Embedded Converters with Unknown-Phase Harmonics. J. Electronic Testing 27(3): 335-350 (2011) |
| c72 | | Elena I. Vatajelu, Alvaro Gómez-Pau, Michel Renovell, Joan Figueras: Transient Noise Failures in SRAM Cells: Dynamic Noise Margin Metric. Asian Test Symposium 2011: 413-418 |
| c71 | | Sandra Irobi, Zaid Al-Ars, Said Hamdioui, Michel Renovell: Influence of parasitic memory effect on single-cell faults in SRAMs. DDECS 2011: 159-162 |
| c70 | | Jesus Moreno, Víctor H. Champac, Michel Renovell: A new methodology for realistic open defect detection probability evaluation under process variations. VTS 2011: 184-189 |
| 2010 | ||
| j42 | | |
| 2009 | ||
| j41 | | M. Wegrzyn, Franc Novak, Anton Biasizzo, Michel Renovell: Functional Testing of Processor Cores in FPGA-Based Applications. Computing and Informatics 28(1): 97-113 (2009) |
| j40 | | Piet Engelke, Bernd Becker, Michel Renovell, Jürgen Schlöffel, Bettina Braitling, Ilia Polian: SUPERB: Simulator utilizing parallel evaluation of resistive bridges. ACM Trans. Design Autom. Electr. Syst. 14(4) (2009) |
| c69 | | Florence Azaïs, Yves Bertrand, Michel Renovell: An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. DDECS 2009: 158-163 |
| c68 | | Nicolas Houarche, Mariane Comte, Michel Renovell, Alejandro Czutro, Piet Engelke, Ilia Polian, Bernd Becker: An Electrical Model for the Fault Simulation of Small Delay Faults Caused by Crosstalk Aggravated Resistive Short Defects. VTS 2009: 21-26 |
| 2008 | ||
| j39 | | Piet Engelke, Ilia Polian, Michel Renovell, Sandip Kundu, Bharath Seshadri, Bernd Becker: On Detection of Resistive Bridging Defects by Low-Temperature and Low-Voltage Testing. IEEE Trans. on CAD of Integrated Circuits and Systems 27(2): 327-338 (2008) |
| j38 | | Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Michel Renovell, Mariane Comte, Omar Chakib: ADC Production Test Technique Using Low-Resolution Arbitrary Waveform Generator. VLSI Design 2008 (2008) |
| c67 | | Alejandro Czutro, Nicolas Houarche, Piet Engelke, Ilia Polian, Mariane Comte, Michel Renovell, Bernd Becker: A Simulator of Small-Delay Faults Caused by Resistive-Open Defects. European Test Symposium 2008: 113-118 |
| c66 | | Florence Azaïs, Laurent Larguier, Yves Bertrand, Michel Renovell: On the Detection of SSN-Induced Logic Errors through On-Chip Monitoring. IOLTS 2008: 233-238 |
| e3 |  | Bernd Straube, Milos Drutarovský, Michel Renovell, Peter Gramata, Mária Fischerová (Eds.): Proceedings of the 11th IEEE Workshop on Design & Diagnostics of Electronic Circuits & Systems (DDECS 2008), Bratislava, Slovakia, April 16-18, 2008. IEEE Computer Society 2008, isbn 978-1-4244-2276-0 |
| e2 | | Marcelo Lubaszewski, Michel Renovell, Rajesh K. Gupta (Eds.): Proceedings of the 21st Annual Symposium on Integrated Circuits and Systems Design, SBCCI 2008, Gramado, Brazil, September 1-4, 2008. ACM 2008, isbn 978-1-60558-231-3 |
| 2007 | ||
| j37 | | Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell: Built-In Self-Test of Field Programmable Analog Arrays based on Transient Response Analysis. J. Electronic Testing 23(6): 497-512 (2007) |
| j36 | | Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: Fully digital test solution for a set of ADCs and DACs embedded in a SIP or SOC. IET Computers & Digital Techniques 1(3): 146-153 (2007) |
| c65 | | Philippe Cauvet, Serge Bernard, Michel Renovell: System-in-Package, a Combination of Challenges and Solutions. European Test Symposium 2007: 193-199 |
| c64 | | Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. European Test Symposium 2007: 211-216 |
| c63 | | Tiago R. Balen, Fernanda Lima Kastensmidt, Marcelo Lubaszewski, Michel Renovell: Single Event Upset in SRAM-based Field Programmable Analog Arrays: Effects and Mitigation. ISVLSI 2007: 192-197 |
| 2006 | ||
| j35 | | Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: A Novel DFT Technique for Testing Complete Sets of ADCs and DACs in Complex SiPs. IEEE Design & Test of Computers 23(3): 234-243 (2006) |
| j34 | | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Automatic Test Pattern Generation for Resistive Bridging Faults. J. Electronic Testing 22(1): 61-69 (2006) |
| j33 | | Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: An Efficient BIST Architecture for Delay Faults in the Logic Cells of Symmetrical SRAM-Based FPGAs. J. Electronic Testing 22(2): 161-172 (2006) |
| j32 | | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive-Bridging and Stuck-At Faults. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2181-2192 (2006) |
| c62 | | Mariane Comte, Satoshi Ohtake, Hideo Fujiwara, Michel Renovell: Electrical Behavior of GOS Fault affected Domino Logic Cell. DELTA 2006: 183-189 |
| c61 | | Vincent Kerzerho, Philippe Cauvet, Serge Bernard, Florence Azaïs, Mariane Comte, Michel Renovell: "Analogue Network of Converters": A DFT Technique to Test a Complete Set of ADCs and DACs Embedded in a Complex SiP or SOC. European Test Symposium 2006: 159-164 |
| c60 | | Tiago R. Balen, José Vicente Calvano, Marcelo Lubaszewski, Michel Renovell: Functional Test of Field Programmable Analog Arrays. VTS 2006: 326-333 |
| 2005 | ||
| j31 | | Florence Azaïs, Marcelo Lubaszewski, Pascal Nouet, Michel Renovell: A Strategy for Optimal Test Point Insertion in Analog Cascaded Filters. J. Electronic Testing 21(1): 9-16 (2005) |
| j30 | | Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Delay Fault Testing of Look-Up Tables in SRAM-Based FPGAs. J. Electronic Testing 21(1): 43-55 (2005) |
| j29 | | Ilia Polian, Piet Engelke, Michel Renovell, Bernd Becker: Modeling Feedback Bridging Faults with Non-Zero Resistance. J. Electronic Testing 21(1): 57-69 (2005) |
| j28 | | Tiago R. Balen, Antonio Q. Andrade, Florence Azaïs, Marcelo Lubaszewski, Michel Renovell: Applying the Oscillation Test Strategy to FPAA's Configurable Analog Blocks. J. Electronic Testing 21(2): 135-146 (2005) |
| j27 | | Adoración Rueda, Michel Renovell, José Luis Huertas: Guest Editorial. J. Electronic Testing 21(3): 203 (2005) |
| j26 | | Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell: Efficiency of Optimized Dynamic Test Flows for ADCs: Sensitivity to Specifications. J. Electronic Testing 21(3): 291-298 (2005) |
| j25 | | Jean Marc Gallière, Michel Renovell, Florence Azaïs, Yves Bertrand: Delay Testing Viability of Gate Oxide Short Defects. J. Comput. Sci. Technol. 20(2): 195-200 (2005) |
| j24 | | Antonio Andrade Jr., Gustavo Vieira, Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell: Built-in self-test of global interconnects of field programmable analog arrays. Microelectronics Journal 36(12): 1112-1123 (2005) |
| c59 | | Ilia Polian, Sandip Kundu, Jean Marc Gallière, Piet Engelke, Michel Renovell, Bernd Becker: Resistive Bridge Fault Model Evolution from Conventional to Ultra Deep Submicron Technologies. VTS 2005: 343-348 |
| c58 | | Gustavo Pereira, Antonio Andrade Jr., Tiago R. Balen, Marcelo Lubaszewski, Florence Azaïs, Michel Renovell: Testing the Interconnect Networks and I/O Resources of Field Programmable Analog Arrays. VTS 2005: 389-394 |
| 2004 | ||
| j23 | | Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell: Efficiency of Spectral-Based ADC Test Flows to Detect Static Errors. J. Electronic Testing 20(3): 257-267 (2004) |
| j22 | | Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell: Correlation Between Static and Dynamic Parameters of A-to-D Converters: In the View of a Unique Test Procedure. J. Electronic Testing 20(4): 375-387 (2004) |
| j21 | | Alex Gonsales, Marcelo Lubaszewski, Luigi Carro, Michel Renovell: A New FPGA for DSP Applications Integrating BIST Capabilities. J. Electronic Testing 20(4): 423-431 (2004) |
| c57 | | Antonio Zenteno, Víctor H. Champac, Michel Renovell, Florence Azaïs: Analysis and Attenuation Proposal in Ground Bounce. Asian Test Symposium 2004: 460-463 |
| c56 | | Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: High Quality TPG for Delay Faults in Look-Up Tables of FPGAs. DELTA 2004: 83-88 |
| c55 | | Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: BIST of Delay Faults in the Logic Architecture of Symmetrical FPGAs. IOLTS 2004: 187-192 |
| c54 | | David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell: Scan Design and Secure Chip. IOLTS 2004: 219-226 |
| c53 | | Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Michel Renovell, Marcelo Lubaszewski: Testing the Configurable Analog Blocks of Field Programmable Analog Arrays. ITC 2004: 893-902 |
| c52 | | Mehdi Baradaran Tahoori, Edward J. McCluskey, Michel Renovell, Philippe Faure: A Multi-Configuration Strategy for an Application Dependent Testing of FPGAs. VTS 2004: 154-170 |
| c51 | | Piet Engelke, Ilia Polian, Michel Renovell, Bharath Seshadri, Bernd Becker: The Pros and Cons of Very-Low-Voltage Testing: An Analysis based on Resistive Bridging Faults. VTS 2004: 171-178 |
| c50 | | Tiago R. Balen, Antonio Andrade Jr., Florence Azaïs, Marcelo Lubaszewski, Michel Renovell: An Approach to the Built-In Self-Test of Field Programmable Analog Arrays. VTS 2004: 383-388 |
| 2003 | ||
| j20 | | Florence Azaïs, Yves Bertrand, Michel Renovell, André Ivanov, Sassan Tabatabaei: An All-Digital DFT Scheme for Testing Catastrophic Faults in PLLs. IEEE Design & Test of Computers 20(1): 60-67 (2003) |
| j19 | | Uros Kac, Franc Novak, Florence Azaïs, Pascal Nouet, Michel Renovell: Extending IEEE Std. 1149.4 Analog Boundary Modules to Enhance Mixed-Signal Test. IEEE Design & Test of Computers 20(2): 32-39 (2003) |
| j18 | | Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand: Modeling the Random Parameters Effects in a Non-Split Model of Gate Oxide Short. J. Electronic Testing 19(4): 377-386 (2003) |
| j17 | | Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell: On-Chip Generation of Ramp and Triangle-Wave Stimuli for ADC BIST. J. Electronic Testing 19(4): 469-479 (2003) |
| j16 | | Michel Renovell: Some Aspects of the Test Generation Problem for an Application-Oriented Test of SRAM-Based FPGAs. Journal of Circuits, Systems, and Computers 12(2): 143-158 (2003) |
| j15 | | Florence Azaïs, Serge Bernard, Yves Bertrand, Mariane Comte, Michel Renovell: A-to-D converters static error detection from dynamic parameter measurement. Microelectronics Journal 34(10): 945-953 (2003) |
| c49 | | Michel Renovell, Jean Marc Gallière, Florence Azaïs, Yves Bertrand: Delay Testing of MOS Transistor with Gate Oxide Short. Asian Test Symposium 2003: 168-173 |
| c48 | | Patrick Girard, Olivier Héron, Serge Pravossoudovitch, Michel Renovell: Defect Analysis for Delay-Fault BIST in FPGAs. IOLTS 2003: 124-128 |
| c47 | | Serge Bernard, Mariane Comte, Florence Azaïs, Yves Bertrand, Michel Renovell: A New Methodology For ADC Test Flow Optimization. ITC 2003: 201-209 |
| c46 | | Piet Engelke, Ilia Polian, Michel Renovell, Bernd Becker: Simulating Resistive Bridging and Stuck-At Faults. ITC 2003: 1051-1059 |
| 2002 | ||
| j14 | | Michel Renovell, Florence Azaïs, Yves Bertrand: Improving Defect Detection in Static-Voltage Testing. IEEE Design & Test of Computers 19(6): 83-89 (2002) |
| c45 | | Michel Renovell, Penelope Faure, Paolo Prinetto, Yervant Zorian: Testing the Unidimensional Interconnect Architecture of Symmetrical SRAM-Based FPGA. DELTA 2002: 297-301 |
| e1 | | Manfred Glesner, Peter Zipf, Michel Renovell (Eds.): Field-Programmable Logic and Applications, Reconfigurable Computing Is Going Mainstream, 12th International Conference, FPL 2002, Montpellier, France, September 2-4, 2002, Proceedings. Lecture Notes in Computer Science 2438, Springer 2002, isbn 3-540-44108-5 |
| 2001 | ||
| j13 | | Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell: A Low-Cost BIST Architecture for Linear Histogram Testing of ADCs. J. Electronic Testing 17(2): 139-147 (2001) |
| j12 | | Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell: Optimizing Sinusoidal Histogram Test for Low Cost ADC BIST. J. Electronic Testing 17(3-4): 255-266 (2001) |
| j11 | | Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: A Discussion on Test Pattern Generation for FPGA - Implemented Circuits. J. Electronic Testing 17(3-4): 283-290 (2001) |
| j10 | | |
| j9 | | André Ivanov, Sumbal Rafiq, Michel Renovell, Florence Azaïs, Yves Bertrand: On the detectability of CMOS floating gate transistor faults. IEEE Trans. on CAD of Integrated Circuits and Systems 20(1): 116-128 (2001) |
| c44 | | Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell: Implementation of a linear histogram BIST for ADCs. DATE 2001: 590-595 |
| c43 | | Serge Bernard, Florence Azaïs, Yves Bertrand, Michel Renovell: Analog BIST Generator for ADC Testing. DFT 2001: 338-346 |
| c42 | | Florence Azaïs, Serge Bernard, Yves Bertrand, Michel Renovell: On-chip Generator of a Saw-Tooth Test Stimulus for ADC BIST. VLSI-SOC 2001: 425-436 |
| c41 | | Michel Renovell: Revisiting the Classical Fault Models through a Detailed Analysis of Realistic Defects. ISQED 2001: 359-364 |
| c40 | | Michel Renovell, Penelope Faure, Jean Michel Portal, Joan Figueras, Yervant Zorian: IS-FPGA : a new symmetric FPGA architecture with implicit scan. ITC 2001: 924-931 |
| c39 | | Michel Renovell, Jean Marc Gallière, Florence Azaïs, Serge Bernard, Yves Bertrand: Boolean and current detection of MOS transistor with gate oxide short. ITC 2001: 1039-1048 |
| c38 | | Florence Azaïs, Serge Bernard, Yves Bertrand, Xavier Michel, Michel Renovell: A Low-Cost Adaptive Ramp Generator for Analog BIST Applications. VTS 2001: 266-271 |
| 2000 | ||
| j8 | | Michel Renovell, Florence Azaïs, J-C. Bodin, Yves Bertrand: Combining Functional and Structural Approaches for Switched-Current Circuit Testing. J. Electronic Testing 16(3): 259-267 (2000) |
| j7 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: An Approach to Minimize the Test Configuration for the Logic Cells of the Xilinx XC4000 FPGAs Family. J. Electronic Testing 16(3): 289-299 (2000) |
| j6 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Local Interconnect Resources of SRAM-Based FPGA's. J. Electronic Testing 16(5): 513-520 (2000) |
| c37 | | Luigi Carro, Érika F. Cota, Marcelo Lubaszewski, Yves Bertrand, Florence Azaïs, Michel Renovell: TI-BIST: a temperature independent analog BIST for switched-capacitor filters. Asian Test Symposium 2000: 78-83 |
| c36 | | Michel Renovell, Jean Michel Portal, Penelope Faure, Joan Figueras, Yervant Zorian: TOF: a tool for test pattern generation optimization of an FPGA application oriented test. Asian Test Symposium 2000: 323-328 |
| c35 | | Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski: Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. DATE 2000: 226-230 |
| c34 | | |
| c33 | | Michel Renovell, Yervant Zorian: Different experiments in test generation for XILINX FPGAs. ITC 2000: 854-862 |
| c32 | | Michel Renovell, Florence Azaïs, Serge Bernard, Yves Bertrand: Hardware Resource Minimization for Histogram-Based ADC BIST. VTS 2000: 247-254 |
| 1999 | ||
| j5 | | Michel Renovell, Florence Azaïs, Yves Bertrand: Detection of Defects Using Fault Model Oriented Test Sequences. J. Electronic Testing 14(1-2): 13-22 (1999) |
| j4 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: Testing the Embedded RAM Modules. J. Electronic Testing 14(1-2): 159-167 (1999) |
| c31 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Minimizing the Number of Test Configurations for Different FPGA Families. Asian Test Symposium 1999: 363-368 |
| c30 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Configurable Interconnect/Logic Interface of SRAM-Based FPGA's. DATE 1999: 618-622 |
| c29 | | Michel Renovell, André Ivanov, Yves Bertrand, Florence Azaïs, Sumbal Rafiq: Optimal conditions for Boolean and current detection of floating gate faults. ITC 1999: 477-486 |
| 1998 | ||
| j3 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Testing the Interconnect of RAM-Based FPGAs. IEEE Design & Test of Computers 15(1): 45-50 (1998) |
| c28 | | Sumbal Rafiq, André Ivanov, Sassan Tabatabaei, Michel Renovell: Testing for Floating Gates Defects in CMOS Circuits. Asian Test Symposium 1998: 228-236 |
| c27 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGA's: Testing the Interconnect/Logic Interface. Asian Test Symposium 1998: 266-271 |
| c26 | | Michel Renovell, Florence Azaïs, J-C. Bodin, Yves Bertrand: BISTing Switched-Current Circuits. Asian Test Symposium 1998: 372-377 |
| c25 | | Florence Azaïs, André Ivanov, Michel Renovell, Yves Bertrand: A Methodology and Design for Effective Testing of Voltage-Controlled Oscillators (VCOs. Asian Test Symposium 1998: 383-387 |
| c24 | | |
| c23 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: RAM-Based FPGA's: A Test Approach for the Configurable Logic. DATE 1998: 82-88 |
| c22 | | Cecilia Metra, Michel Renovell, G. Mojoli, Jean Michel Portal, Sandro Pastore, Joan Figueras, Yervant Zorian, Davide Salvi, Giacomo R. Sechi: Novel Technique for Testing FPGAs. DATE 1998: 89-94 |
| c21 | | Michel Renovell, Florence Azaïs, Yves Bertrand: Optimized Implementations of the Multi-Configuration DFT Technique for Analog Circuits. DATE 1998: 815-821 |
| c20 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-Based FPGAs: A Fault Model for the Configurable Logig Modules. FPL 1998: 139-148 |
| c19 | | Karl-Erwin Großpietsch, Jacob A. Abraham, Johannes Maier, Hans-Dieter Kochs, Michel Renovell: From Dependable Computing Systems to Computing for Integrated Dependable Systems? (Panel). FTCS 1998: 296-301 |
| c18 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: SRAM-based FPGA's: testing the LUT/RAM modules. ITC 1998: 1102-1111 |
| c17 | | Florence Azaïs, Michel Renovell, Yves Bertrand, J-C. Bodin: Design-For-Testability for Switched-Current Circuits. VTS 1998: 370-375 |
| 1997 | ||
| c16 | | Michel Renovell, Jean Michel Portal, Joan Figueras, Yervant Zorian: Test Pattern and Test Configuration Generation Methodology for the Logic of RAM-Based FPGA. Asian Test Symposium 1997: 254- |
| c15 | | Michel Renovell, Florence Azaïs, Yves Bertrand: On-chip analog output response compaction. ED&TC 1997: 568-572 |
| c14 | | |
| c13 | | Michel Renovell, Joan Figueras, Yervant Zorian: Test of RAM-based FPGA: methodology and application to the interconnect. VTS 1997: 230-237 |
| 1996 | ||
| c12 | | Michel Renovell, P. Huc, Yves Bertrand: The Logic Threshold Based Voting: A Model for Local Feedback Bridging Fault. EDCC 1996: 205-213 |
| c11 | | Michel Renovell, Florence Azaïs, Yves Bertrand: The multi-configuration: A DFT technique for analog circuits. VTS 1996: 54-59 |
| c10 | | Michel Renovell, P. Huc, Yves Bertrand: Bridging fault coverage improvement by power supply control. VTS 1996: 338-343 |
| 1995 | ||
| j2 | | Joan Figueras, Michel Renovell: Current testing in dynamic CMOS circuits. J. Electronic Testing 6(1): 127-131 (1995) |
| c9 | | Michel Renovell, P. Huc, Yves Bertrand: Serial transistor network modeling for bridging fault simulation. Asian Test Symposium 1995: 100-106 |
| c8 | | Michel Renovell, Florence Azaïs, Yves Bertrand: A design-for-test technique for multistage analog circuits. Asian Test Symposium 1995: 113-119 |
| c7 | | S. Lavabre, Yves Bertrand, Michel Renovell, Christian Landrault: Test configurations to enhance the testability of sequential circuits. Asian Test Symposium 1995: 160-168 |
| c6 | | Michel Renovell, P. Huc, Yves Bertrand: The concept of resistance interval: a new parametric model for realistic resistive bridging fault. VTS 1995: 184-189 |
| 1994 | ||
| c5 | | Michel Renovell, P. Huc, Yves Bertrand: The Configuration Ratio: A Model for Simulating CMOS Intra-Gate Bridge with Variable Logic Thresholds. EDCC 1994: 165-177 |
| c4 | | |
| 1993 | ||
| c3 | | Michel Renovell, Joan Figueras: Current Testing Viability in Dynamic CMOS Circuits. DFT 1993: 207-214 |
| c2 | | Yves Bertrand, Frédéric Bancel, Michel Renovell: Multiconfiguration Technique to Reduce Test Duration for Sequential Circuits. ITC 1993: 989-997 |
| c1 | | Yves Bertrand, Frédéric Bancel, Michel Renovell: A DFT Technique to Improve ATPG Efficiency for Sequential Circuits. VLSI Design 1993: 51-54 |
| 1992 | ||
| j1 | | Michel Renovell, Gaston Cambon: Electrical analysis and modeling of floating-gate fault. IEEE Trans. on CAD of Integrated Circuits and Systems 11(11): 1450-1458 (1992) |
Colors in the list of coauthors
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