Phillip Restle

Haifeng Qian, Phillip J. Restle, Joseph N. Kozhaya, Clifford L. Gunion: Subtractive Router for Tree-Driven-Grid Clocks. IEEE Trans. on CAD of Integrated Circuits and Systems 31(6): 868-877 (2012)

Dieter F. Wendel, Ronald N. Kalla, James D. Warnock, Robert Cargnoni, Sam G. Chu, Joachim G. Clabes, Daniel Dreps, David Hrusecky, Joshua Friedrich, Md. Saiful Islam, James A. Kahle, Jens Leenstra, Gaurav Mittal, Jose Paredes, Juergen Pille, Phillip J. Restle, Balaram Sinharoy, George Smith, William J. Starke, Scott Taylor, James Van Norstrand, Stephen Weitzel, Phillip G. Williams, Victor V. Zyuban: POWER7™, a Highly Parallel, Scalable Multi-Core High End Server Processor. J. Solid-State Circuits 46(1): 145-161 (2011)

Joseph N. Kozhaya, Phillip Restle, Haifeng Qian: Myth busters: Microprocessor clocking is from Mars, ASICs clocking is from Venus. ICCAD 2011: 271-275

Cliff N. Sze, Phillip Restle, Gi-Joon Nam, Charles J. Alpert: Ispd2009 clock network synthesis contest. ISPD 2009: 149-150

Robert L. Franch, Phillip Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, G. Salem: On-chip Timing Uncertainty Measurements on IBM Microprocessors. ITC 2008: 1-7

Rex Berridge, Robert M. Averill III, Arnold E. Barish, Michael A. Bowen, Peter J. Camporese, Jack DiLullo, Peter E. Dudley, Joachim Keinert, David W. Lewis, Robert D. Morel, Thomas E. Rosser, Nicole S. Schwartz, Philip Shephard, Howard H. Smith, Dave Thomas, Phillip J. Restle, John R. Ripley, Stephen L. Runyon, Patrick M. Williams: IBM POWER6 microprocessor physical design and design methodology. IBM Journal of Research and Development 51(6): 685-714 (2007)

Robert L. Franch, Phillip Restle, James K. Norman, William V. Huott, Joshua Friedrich, R. Dixon, Steve Weitzel, K. van Goor, G. Salem: On-chip timing uncertainty measurements on IBM microprocessors. ITC 2007: 1-7

Phillip Restle, Kenneth L. Shepard: New Prospects for Clocking Synchronous and Quasi-Asynchronous Systems. ASYNC 2005

Gerald G. Lopez, Giovanni Fiorenza, Thomas J. Bucelot, Phillip Restle, Mary Yvonne Lanzerotti: Characterization of the impact of interconnect design on the capacitive load driven by a global clock distribution. ACM Great Lakes Symposium on VLSI 2005: 38-43

Joachim G. Clabes, Joshua Friedrich, Mark Sweet, Jack DiLullo, Sam G. Chu, Donald W. Plass, James Dawson, Paul Muench, Larry Powell, Michael S. Floyd, Balaram Sinharoy, Mike Lee, Michael Goulet, James Wagoner, Nicole S. Schwartz, Stephen L. Runyon, Gary Gorman, Phillip Restle, Ronald N. Kalla, Joseph McGill, J. Steve Dodson: Design and implementation of the POWER5 microprocessor. DAC 2004: 670-672

Steven C. Chan, Kenneth L. Shepard, Phillip Restle: Design of Resonant Global Clock Distributions. ICCD 2003: 248-253

James D. Warnock, John M. Keaty, John G. Petrovick, Joachim G. Clabes, Charles J. Kircher, Byron Krauter, Phillip Restle, Brian A. Zoric, Carl J. Anderson: The circuit and physical design of the POWER4 microprocessor. IBM Journal of Research and Development 46(1): 27-52 (2002)

Phillip Restle, Albert E. Ruehli, Steven G. Walker, George Papadopoulos: Full-wave PEEC time-domain method for the modeling of on-chipinterconnects. IEEE Trans. on CAD of Integrated Circuits and Systems 20(7): 877-886 (2001)

Phillip Restle: Technical Visualizations in VLSI Design. DAC 2001: 494-499

Phillip Restle, Albert E. Ruehli, Steven G. Walker: Multi-GHz interconnect effects in microprocessors. ISPD 2001: 93-97

Phillip Restle, Albert E. Ruehli, Steven G. Walker: Dealing with Inductance in High-Speed Chip Design. DAC 1999: 904-909

Phillip Restle, Joel R. Phillips, Ibrahim M. Elfadel: Interconnect in high speed designs: problems, methodologies and tools. ICCAD 1998: 4