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Lluis Ribas
2000 – 2009
- 2005
[c8]Antoni Portero, Lluis Ribas, Jordi Carrabina: Hardware Synthesis of Parallel Machines from SystemC. FDL 2005: 353-361- 2003
- [c7]
1990 – 1999
- 1999
- [c6]Lluis Ribas, Jordi Carrabina: Digital MOS Circuit Partitioning with Symbolic Modeling. DATE 1999: 503-508
- 1998
- [c5]Lluis Ribas, Jordi Carrabina: On the Reuse of Symbolic Simulation Results for Incremental Equivalence Verification of Switch-Level Circuits. DATE 1998: 624-629
- 1997
- [j2]Jordi Riera, Lluis Ribas, A. Josep Velasco, Jordi Carrabina: Deriving cost functions from cell libraries and real ICs to allow real area-power-delay trade-off in early stages of logic synthesis. Journal of Systems Architecture 43(1-5): 119-122 (1997)
- 1995
- [c4]Lluis Ribas, Jordi Carrabina: Analysis of Switch-Level Faults by Symbolic Simulation. DAC 1995: 352-357
- [c3]Lluis Ribas, Jordi Carrabina: Symbolic Analysis for Fault Detection in Switch-Level Circuits. ISCAS 1995: 1235-1238
- 1994
- [c2]A. Josep Velasco, Lluis Ribas, Elena Valderrama, R. Gracia: A Fuzzy Rule Interpreter to Build Expert Systems Based on Fuzzy Logic. An Application in Company Diagnosis. Fuzzy Days 1994: 433-438
- [c1]Rafael Peset Llopis, Lluis Ribas, Jordi Carrabina: Short Destabilizing Paths in Timing Verification. ICCD 1994: 160-163
- 1993
- [j1]Lluis Ribas, Jordi Riera, J. M. Pérez, Joaquín Saiz, Jordi Carrabina, Lluís Terés: Automatic pattern generation for the electrical characterization of digital modules. Microprocessing and Microprogramming 39(2-5): 255-258 (1993)
Coauthor Index
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last updated on 2012-12-02 21:45 CET by the dblp team