Jude A. Rivers

Pradip Bose, Alper Buyuktosunoglu, John A. Darringer, Meeta Sharma Gupta, Michael B. Healy, Hans M. Jacobson, Indira Nair, Jude A. Rivers, Jeonghee Shin, Augusto Vega, Alan J. Weger: Power management of multi-core chips: Challenges and pitfalls. DATE 2012: 977-982

Jude A. Rivers, Meeta Sharma Gupta, Jeonghee Shin, Prabhakar Kudva, Pradip Bose: Error Tolerance in Server Class Processors. IEEE Trans. on CAD of Integrated Circuits and Systems 30(7): 945-959 (2011)

Guangyu Sun, Eren Kursun, Jude A. Rivers, Yuan Xie: Exploring the vulnerability of CMPs to soft errors with 3D stacked non-volatile memory. ICCD 2011: 366-372

Pradip Bose, Alper Buyuktosunoglu, Chen-Yong Cher, John A. Darringer, Meeta Sharma Gupta, Hendrik F. Hamann, Hans M. Jacobson, Prabhakar Kudva, Eren Kursun, Niti Madan, Indira Nair, Jude A. Rivers, Jeonghee Shin, Alan J. Weger, Victor V. Zyuban: Power-efficient, reliable microprocessor architectures: modeling and design methods. ACM Great Lakes Symposium on VLSI 2010: 299-304

Nak Hee Seong, Dong Hyuk Woo, Vijayalakshmi Srinivasan, Jude A. Rivers, Hsien-Hsin S. Lee: SAFER: Stuck-At-Fault Error Recovery for Memories. MICRO 2010: 115-124

Jude A. Rivers, Prabhakar Kudva: Reliability Challenges and System Performance at the Architecture Level. IEEE Design & Test of Computers 26(6): 62-73 (2009)

Moinuddin K. Qureshi, Vijayalakshmi Srinivasan, Jude A. Rivers: Scalable high performance main memory system using phase-change memory technology. ISCA 2009: 24-33

Meeta Sharma Gupta, Jude A. Rivers, Pradip Bose, Gu-Yeon Wei, David Brooks: Tribeca: design for PVT variations with local recovery and fine-grained adaptation. MICRO 2009: 435-446

Jude A. Rivers, Pradip Bose, Prabhakar Kudva, John-David Wellman, Pia N. Sanda, Ethan H. Cannon, Luiz C. Alves: Phaser: Phased methodology for modeling the system-level effects of soft errors. IBM Journal of Research and Development 52(3): 293-306 (2008)

Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers: Online Estimation of Architectural Vulnerability Factor for Soft Errors. ISCA 2008: 341-352

Pradeep Ramachandran, Sarita V. Adve, Pradip Bose, Jude A. Rivers: Metrics for Architecture-Level Lifetime Reliability Analysis. ISPASS 2008: 202-212

Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers: Architecture-Level Soft Error Analysis: Examining the Limits of Common Assumptions. DSN 2007: 266-275

Jeonghee Shin, Victor V. Zyuban, Zhigang Hu, Jude A. Rivers, Pradip Bose: A Framework for Architecture-Level Lifetime Reliability Modeling. DSN 2007: 534-543

Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers: Lifetime Reliability: Toward an Architectural Solution. IEEE Micro 25(3): 70-80 (2005)

Xiaodong Li, Sarita V. Adve, Pradip Bose, Jude A. Rivers: SoftArch: An Architecture Level Tool for Modeling and Analyzing Soft Errors. DSN 2005: 496-505

Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers: Exploiting Structural Duplication for Lifetime Reliability Enhancement. ISCA 2005: 520-531

Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers: The Impact of Technology Scaling on Lifetime Reliability. DSN 2004: 177-

Jayanth Srinivasan, Sarita V. Adve, Pradip Bose, Jude A. Rivers: The Case for Lifetime Reliability-Aware Microprocessors. ISCA 2004: 276-287

Jude A. Rivers, Sameh W. Asaad, John-David Wellman, Jaime H. Moreno: Reducing instruction fetch energy with backwards branch control information and buffering. ISLPED 2003: 322-325

Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson: Active Management of Data Caches by Exploiting Reuse Information. IEEE Trans. Computers 48(11): 1244-1259 (1999)

Edward S. Tam, Jude A. Rivers, Vijayalakshmi Srinivasan, Gary S. Tyson, Edward S. Davidson: Evaluating the performance of active cache management schemes. ICCD 1998: 368-375

Jude A. Rivers, Edward S. Tam, Gary S. Tyson, Edward S. Davidson, Matthew K. Farrens: Utilizing Reuse Information in Data Cache Management. International Conference on Supercomputing 1998: 449-456

Edward S. Tam, Jude A. Rivers, Gary S. Tyson, Edward S. Davidson: mlcache: A Flexible Multi-Lateral Cache Simulator. MASCOTS 1998: 19-26

Jude A. Rivers, Edward S. Tam, Edward S. Davidson: On Effective Data Supply For Multi-Issue Processors. ICCD 1997: 519-528

Jude A. Rivers, Gary S. Tyson, Edward S. Davidson, Todd M. Austin: On High-Bandwidth Data Cache Design for Multi-Issue Processors. MICRO 1997: 46-56

Jude A. Rivers, Edward S. Davidson: Performance Issues in Integrating Temporality-Based Caching with Prefetching. Perform. Eval. 27/28(4): 189-207 (1996)

Jude A. Rivers, Edward S. Davidson: Reducing Conflicts in Direct-Mapped Caches with a Temporality-Based Design. ICPP, Vol. 1 1996: 154-163