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Ronny Ronen
2010 – today
- 2010
[e1]André Seznec, Uri C. Weiser, Ronny Ronen (Eds.): 37th International Symposium on Computer Architecture (ISCA 2010), June 19-23, 2010, Saint-Malo, France. ACM 2010, ISBN 978-1-4503-0053-7
2000 – 2009
- 2009
- [j5]Amit Golander, Shlomo Weiss, Ronny Ronen: Synchronizing Redundant Cores in a Dynamic DMR Multicore Architecture. IEEE Trans. on Circuits and Systems 56-II(6): 474-478 (2009)
- [c12]Ronny Ronen: Larrabee: a many-core Intel architecture for visual computing. Conf. Computing Frontiers 2009: 225
- [c11]Shoumeng Yan, Xiaocheng Zhou, Ying Gao, Hu Chen, Sai Luo, Peinan Zhang, Naveen Cherukuri, Ronny Ronen, Bratin Saha: Terascale chip multiprocessor memory hierarchy and programming model. HiPC 2009: 150-159
- [c10]Bratin Saha, Xiaocheng Zhou, Hu Chen, Ying Gao, Shoumeng Yan, Mohan Rajagopalan, Jesse Fang, Peinan Zhang, Ronny Ronen, Avi Mendelson: Programming model for a heterogeneous x86 platform. PLDI 2009: 431-440
- 2008
- [j4]Amit Golander, Shlomo Weiss, Ronny Ronen: DDMR: Dynamic and Scalable Dual Modular Redundancy with Short Validation Intervals. Computer Architecture Letters 7(2): 65-68 (2008)
- 2007
- [j3]Ronny Ronen, Antonio González: Guest Editors' Introduction: Micro's Top Picks from the Microarchitecture Conferences. IEEE Micro 27(1): 8-11 (2007)
- 2004
- [c9]Ed Grochowski, Ronny Ronen, John Paul Shen, Hong Wang: Best of Both Latency and Throughput. ICCD 2004: 236-243
- 2003
- [j2]Aviad Cohen, Lev Finkelstein, Avi Mendelson, Ronny Ronen, Dmitry Rudoy: On Estimating Optimal Performance of CPU Dynamic Thermal Management. Computer Architecture Letters 2 (2003)
- [j1]Baruch Solomon, Avi Mendelson, Ronny Ronen, Doron Orenstein, Yoav Almog: Micro-operation cache: a power aware frontend for variable instruction length ISA. IEEE Trans. VLSI Syst. 11(5): 801-811 (2003)
- [c8]Roni Rosner, Micha Moffie, Yiannakis Sazeides, Ronny Ronen: Selecting long atomic traces for high coverage. ICS 2003: 2-11
- 2001
- [c7]Roni Rosner, Avi Mendelson, Ronny Ronen: Filtering Techniques to Improve Trace-Cache Efficiency. IEEE PACT 2001: 37-48
- [c6]Baruch Solomon, Avi Mendelson, Doron Orenstein, Yoav Almog, Ronny Ronen: Micro-operation cache: a power aware frontend for the variable instruction length ISA. ISLPED 2001: 4-9
- 2000
- [c5]Stéphan Jourdan, Lihu Rappoport, Yoav Almog, Mattan Erez, Adi Yoaz, Ronny Ronen: eXtended Block Cache. HPCA 2000: 61-70
- [c4]Michael Bekerman, Adi Yoaz, Freddy Gabbay, Stéphan Jourdan, Maxim Kalaev, Ronny Ronen: Early load address resolution via register tracking. ISCA 2000: 306-315
1990 – 1999
- 1999
- [c3]Adi Yoaz, Mattan Erez, Ronny Ronen, Stéphan Jourdan: Speculation Techniques for Improving Load Related Instruction Scheduling. ISCA 1999: 42-53
- [c2]Michael Bekerman, Stéphan Jourdan, Ronny Ronen, Gilad Kirshenboim, Lihu Rappoport, Adi Yoaz, Uri C. Weiser: Correlated Load-Address Predictors. ISCA 1999: 54-63
- 1998
- [c1]Stéphan Jourdan, Ronny Ronen, Michael Bekerman, Bishara Shomar, Adi Yoaz: A Novel Renaming Scheme to Exploit Value Temporal Locality Through Physical Register Reuse and Unification. MICRO 1998: 216-225
Coauthor Index
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last updated on 2012-12-02 21:23 CET by the dblp team