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Partha S. Roop
2010 – today
- 2013
[c37]Sidharta Andalam, Alain Girault, Roopak Sinha, Partha S. Roop, Jan Reineke: Precise timing analysis for direct-mapped caches. DAC 2013: 148- 2012
- [j20]Li Hsien Yoong, Partha S. Roop, Zoran Salcic: Implementing constrained cyber-physical systems with IEC 61499. ACM Trans. Embedded Comput. Syst. 11(4): 78 (2012)
- [j19]Li Hsien Yoong, Gareth Shaw, Partha S. Roop, Zoran Salcic: Synthesizing Globally Asynchronous Locally Synchronous Systems With IEC 61499. IEEE Transactions on Systems, Man, and Cybernetics, Part C 42(6): 1465-1477 (2012)
- [c36]Roopak Sinha, Partha S. Roop, Zoran Salcic, Samik Basu: Correct-by-construction multi-component SoC design. DATE 2012: 647-652
- [c35]K. Nicholas, Zeeshan Ejaz Bhatti, Partha S. Roop: Model-driven development of industrial embedded systems: Challenges faced and lessons learnt. ETFA 2012: 1-4
- [c34]Zachary J. Oster, Syed Adeel Ali, Ganesh Ram Santhanam, Samik Basu, Partha S. Roop: A Service Composition Framework Based on Goal-Oriented Requirements Engineering, Model Checking, and Qualitative Preference Analysis. ICSOC 2012: 283-297
- [c33]Li Hsien Yoong, Zeeshan Ejaz Bhatti, Partha S. Roop: Combining IEC 61499 Model-Based Design with Component-Based Architecture for Robotics. SIMPAR 2012: 349-360
- 2011
- [j18]Ivan Radojevic, Zoran Salcic, Partha S. Roop: Design of Distributed Heterogeneous Embedded Systems in DDFCharts. IEEE Trans. Parallel Distrib. Syst. 22(2): 296-308 (2011)
- [c32]Matthew Kuo, Roopak Sinha, Partha S. Roop: Efficient WCRT analysis of synchronous programs using reachability. DAC 2011: 480-485
- [c31]Sidharta Andalam, Partha S. Roop, Alain Girault: Pruning infeasible paths for tight WCRT analysis of synchronous programs. DATE 2011: 204-209
- [c30]Simon Yuan, Li Hsien Yoong, Partha S. Roop: Compiling Esterel for Multi-core Execution. DSD 2011: 727-735
- [c29]Syed Adeel Ali, Partha S. Roop, Ian Warren, Zeeshan Ejaz Bhatti: Unified management of control flow and data mismatches in web service composition. SOSE 2011: 93-101
- 2010
- [j17]Avinash Malik, Zoran Salcic, Partha S. Roop, Alain Girault: SystemJ: A GALS language for system level design. Computer Languages, Systems & Structures 36(4): 317-344 (2010)
- [j16]Li Hsien Yoong, Partha S. Roop: Verifying IEC 61499 Function Blocks Using Esterel. Embedded Systems Letters 2(1): 1-4 (2010)
- [c28]Sidharta Andalam, Partha S. Roop, Alain Girault: Deterministic, predictable and light-weight multithreading using PRET-C. DATE 2010: 1653-1656
- [c27]Sidharta Andalam, Partha S. Roop, Alain Girault: Predictable multithreading of embedded applications using PRET-C. MEMOCODE 2010: 159-168
2000 – 2009
- 2009
- [j15]Simon Yuan, Li Hsien Yoong, Sidharta Andalam, Partha S. Roop, Zoran Salcic: A New Multithreaded Architecture Supporting Direct Execution of Esterel. EURASIP J. Emb. Sys. 2009 (2009)
- [j14]Simon Yuan, Sidharta Andalam, Li Hsien Yoong, Partha S. Roop, Zoran A. Salcic: STARPro - A new multithreaded direct execution platform for Esterel. Electr. Notes Theor. Comput. Sci. 238(1): 37-55 (2009)
- [j13]Li Hsien Yoong, Partha S. Roop, Valeriy Vyatkin, Zoran A. Salcic: A Synchronous Approach for IEC 61499 Function Block Implementation. IEEE Trans. Computers 58(12): 1599-1614 (2009)
- [j12]Avinash Malik, Zoran A. Salcic, Partha S. Roop: SystemJ compilation using the tandem virtual machine approach. ACM Trans. Design Autom. Electr. Syst. 14(3) (2009)
- [c26]Partha S. Roop, Alain Girault, Roopak Sinha, Gregor Goessler: Specification Enforcing Refinement for Convertibility Verification. ACSD 2009: 148-157
- [c25]Partha S. Roop, Sidharta Andalam, Reinhard von Hanxleden, Simon Yuan, Claus Traulsen: Tight WCRT analysis of synchronous C programs. CASES 2009: 205-214
- [c24]Roopak Sinha, Partha S. Roop, Samik Basu, Zoran Salcic: Multi-clock Soc design using protocol conversion. DATE 2009: 123-128
- [c23]Gareth Shaw, Partha S. Roop, Zoran Salcic: A Hierarchical and Concurrent Approach for IEC 61499 Function Blocks. ETFA 2009: 1-8
- 2008
- [j11]Roopak Sinha, Partha S. Roop, Samik Basu: SoC Design Approach Using Convertibility Verification. EURASIP J. Emb. Sys. 2008 (2008)
- [j10]Roopak Sinha, Partha S. Roop, Samik Basu: A Model Checking Approach to Protocol Conversion. Electr. Notes Theor. Comput. Sci. 203(4): 81-94 (2008)
- [c22]Roopak Sinha, Partha S. Roop, Samik Basu: A Module Checking Based Converter Synthesis Approach for SoCs. VLSI Design 2008: 492-501
- 2007
- [j9]Samik Basu, Partha S. Roop, Roopak Sinha: Local Module Checking for CTL Specifications. Electr. Notes Theor. Comput. Sci. 176(2): 125-141 (2007)
- [j8]Hai-Feng Guo, Miao Liu, Partha S. Roop, C. R. Ramakrishnan, I. V. Ramakrishnan: Precise specification matching for adaptive reuse in embedded systems. J. Applied Logic 5(2): 333-355 (2007)
- [c21]Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: McCharts and Multiclock FSMs for modeling large scale systems. MEMOCODE 2007: 3-12
- 2006
- [j7]Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Modeling Embedded Systems: From SystemC and Esterel to DFCharts. IEEE Design & Test of Computers 23(5): 348-358 (2006)
- [j6]Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari: HiDRA - A reactive multiprocessor architecture for heterogeneous embedded systems. Microprocessors and Microsystems 30(2): 72-85 (2006)
- [c20]Flavius Gruian, Partha S. Roop, Zoran A. Salcic, Ivan Radojevic: The SystemJ approach to system-level design. MEMOCODE 2006: 149-158
- [c19]Zoran A. Salcic, Flavius Gruian, Partha S. Roop, Alif Wahid: A Scheduler Support Unit for Reactive Microprocessors. RTCSA 2006: 368-372
- [c18]Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Design of Heterogeneous Embedded Systems Using DFCharts Model of Computation. VLSI Design 2006: 461-464
- 2005
- [j5]Roopak Sinha, Partha S. Roop, Bakhadyr Khoussainov: Adaptive Verification using Forced Simulation. Electr. Notes Theor. Comput. Sci. 141(3): 171-197 (2005)
- [j4]Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: A New Model for Heterogeneous Embedded Systems - What Esterel and SyncCharts Need to Become a Suitable Specification Platform. International Journal of Software Engineering and Knowledge Engineering 15(2): 405-410 (2005)
- [c17]Zoran A. Salcic, Dong Hui, Partha S. Roop, Morteza Biglari-Abhari: REMIC: design of a reactive embedded microprocessor core. ASP-DAC 2005: 977-981
- [c16]Ivan Radojevic, Zoran A. Salcic, Partha S. Roop: Modelling Heterogeneous Embedded Systems in DFCarts. FDL 2005: 441-453
- [c15]Robi Malik, Partha S. Roop: Adaptive Techniques for Specification Matching in Embedded Systems: A Comparative Study. IFM 2005: 33-52
- 2004
- [j3]Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli: REFLIX: a processor core with native support for control-dominated embedded applications. Microprocessors and Microsystems 28(1): 13-25 (2004)
- [c14]Zoran A. Salcic, Partha S. Roop, Dong Hui, Ivan Radojevic: HiDRA: A New Architecture for Heterogeneous Embedded Systems. ESA/VLSI 2004: 164-170
- [c13]Partha S. Roop, Zoran A. Salcic, M. W. Sajeewa Dayaratne: Towards direct execution of esterel programs on reactive processors. EMSOFT 2004: 240-248
- [c12]Zoran A. Salcic, Partha S. Roop: Customizing Processor Cores to Support Reactivity. ERSA 2004: 194-202
- 2003
- [c11]Partha S. Roop, Zoran A. Salcic, Morteza Biglari-Abhari, Abbas Bigdeli: A New Reactive Processor with Architectural Support for Control Dominated Embedded Systems. VLSI Design 2003: 189-194
- [c10]Rick Mugridge, Bruce A. MacDonald, Partha S. Roop: A Customer Test Generator for Web-Based Systems. XP 2003: 189-197
- [c9]Rick Mugridge, Bruce A. MacDonald, Partha S. Roop, Ewan D. Tempero: Five Challenges in Teaching XP. XP 2003: 406-409
- 2002
- [c8]Zoran A. Salcic, Partha S. Roop, Morteza Biglari-Abhari, Abbas Bigdeli: REFLIX: A Processor Core for Reactive Embedded Applications. FPL 2002: 945-945
- [c7]Partha S. Roop, Arcot Sowmya, S. Ramesh: k-time Forced Simulation: A Formal Verification Technique for IP Reuse. ICCD 2002: 50-55
- 2001
- [j2]Partha S. Roop, Arcot Sowmya, S. Ramesh: Forced simulation: A technique for automating component reuse in embedded systems. ACM Trans. Design Autom. Electr. Syst. 6(4): 602-628 (2001)
- [c6]Partha S. Roop, Arcot Sowmya, S. Ramesh: A formal approach to component based development of synchronous programs. ASP-DAC 2001: 421-424
- 2000
- [c5]Partha S. Roop, Arcot Sowmya, S. Ramesh: Automated Component Adaptation by Forced Simulation. ACAC 2000: 74-81
- [c4]Partha S. Roop, Arcot Sowmya, S. Ramesh: Automatic Component Matching Using Forced Simulation. VLSI Design 2000: 64-69
1990 – 1999
- 1998
- [c3]Partha S. Roop, Arcot Sowmya: Hidden time model for specification and verification of embedded systems. ECRTS 1998: 98-105
- [c2]Partha S. Roop, Arcot Sowmya: CFSMcharts: A New Language for Microprocessor Based system Design. VLSI Design 1998: 342-346
- 1996
- [j1]Raj S. Mitra, Partha S. Roop, Anupam Basu: A new algorithm for implementation of design functions by available devices. IEEE Trans. VLSI Syst. 4(2): 170-180 (1996)
- 1995
- [c1]Raj S. Mitra, Partha S. Roop, Anupam Basu: Implementation of design functions by available devices: a new algorithm. VLSI Design 1995: 30-35
Coauthor Index
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last updated on 2013-05-28 21:39 CEST by the dblp team