| 2012 | ||
|---|---|---|
| c12 | Adam C. Faust, Rajan Narasimha, Karan S. Bhatia, Ankit Srivastava, Chhay Kong, Hyeon-Min Bae, Elyse Rosenbaum, Naresh R. Shanbhag: FEC-based 4 Gb/s backplane transceiver in 90nm CMOS. CICC 2012: 1-4 | |
| 2011 | ||
| c11 | Elyse Rosenbaum, Vrashank Shukla, Min-Sun Keel: ESD protection networks for 3D integrated circuits. 3DIC 2011: 1-7 | |
| c10 | Nicholas Olson, Nathan Jack, Vrashank Shukla, Elyse Rosenbaum: CDM-ESD induced damage in components using stacked-die packaging. CICC 2011: 1-4 | |
| 2009 | ||
| j12 | Farzan Farbiz, Elyse Rosenbaum: A new compact model for external latchup. Microelectronics Reliability 49(12): 1447-1454 (2009) | |
| c9 | Elyse Rosenbaum, Hyeon-Min Bae, Karan S. Bhatia, Adam C. Faust: Moving signals on and off chip. CICC 2009: 585-592 | |
| 2006 | ||
| j11 | Hongmei Li, Cole E. Zemke, Giorgos Manetas, Vladimir I. Okhmatovski, Elyse Rosenbaum, Andreas C. Cangellaris: An automated and efficient substrate noise analysis tool. IEEE Trans. on CAD of Integrated Circuits and Systems 25(3): 454-468 (2006) | |
| 2005 | ||
| j10 | Sami Hyvonen, Sopan Joshi, Elyse Rosenbaum: Comprehensive ESD protection for RF inputs. Microelectronics Reliability 45(2): 245-254 (2005) | |
| c8 | Elyse Rosenbaum, Sami Hyvonen: On-chip ESD protection for RF I/Os: devices, circuits and models. ISCAS (2) 2005: 1202-1205 | |
| 2004 | ||
| j9 | Rouwaida Kanj, Elyse Rosenbaum: Critical evaluation of SOI design guidelines. IEEE Trans. VLSI Syst. 12(9): 885-894 (2004) | |
| c7 | Rouwaida Kanj, Timothy Lehner, Bhavna Agrawal, Elyse Rosenbaum: Noise characterization of static CMOS gates. DAC 2004: 888-893 | |
| 2003 | ||
| j8 | Sopan Joshi, Elyse Rosenbaum: Simulator-independent compact modeling of vertical npn transistors for ESD and RF circuit simulation. Microelectronics Reliability 43(7): 1021-1027 (2003) | |
| 2002 | ||
| c6 | Hongmei Li, Jorge Carballido, Harry H. Yu, Vladimir I. Okhmatovski, Elyse Rosenbaum, Andreas C. Cangellaris: Comprehensive frequency-dependent substrate noise analysis using boundary element methods. ICCAD 2002: 2-9 | |
| c5 | Rouwaida Kanj, Elyse Rosenbaum: A critical look at design guidelines for SOI logic gates. ISCAS (3) 2002: 261-264 | |
| 2001 | ||
| j7 | Elyse Rosenbaum, Jie Wu: Trap generation and breakdown processes in very thin gate oxides. Microelectronics Reliability 41(5): 625-632 (2001) | |
| j6 | Jie Wu, Patrick Juliano, Elyse Rosenbaum: Breakdown and latent damage of ultra-thin gate oxides under ESD stress conditions. Microelectronics Reliability 41(11): 1771-1779 (2001) | |
| j5 | Yu Wang, Patrick Juliano, Sopan Joshi, Elyse Rosenbaum: Electrothermal model for simulation of bulk-Si and SOI diodes in ESD protection circuits. Microelectronics Reliability 41(11): 1781-1787 (2001) | |
| 2000 | ||
| j4 | Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang: Interconnect thermal modeling for accurate simulation of circuittiming and reliability. IEEE Trans. on CAD of Integrated Circuits and Systems 19(2): 197-205 (2000) | |
| 1999 | ||
| c4 | Tong Li, Ching-Han Tsai, Elyse Rosenbaum, Sung-Mo Kang: Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation. DAC 1999: 549-554 | |
| c3 | Danqing Chen, Erhong Li, Elyse Rosenbaum, Sung-Mo Kang: Interconnect thermal modeling for determining design limits on current density. ISPD 1999: 172-178 | |
| 1998 | ||
| j3 | Yi-Kan Cheng, Prasun Raha, Chin-Chi Teng, Elyse Rosenbaum, Sung-Mo Kang: ILLIADS-T: an electrothermal timing simulator for temperature-sensitive reliability diagnosis of CMOS VLSI chips. IEEE Trans. on CAD of Integrated Circuits and Systems 17(8): 668-681 (1998) | |
| 1997 | ||
| j2 | Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang: iTEM: a temperature-dependent electromigration reliability diagnosis tool. IEEE Trans. on CAD of Integrated Circuits and Systems 16(8): 882-893 (1997) | |
| 1996 | ||
| c2 | Yi-Kan Cheng, Chin-Chi Teng, Abhijit Dharchoudhury, Elyse Rosenbaum, Sung-Mo Kang: iCET: A Complete Chip-Level Thermal Reliability Diagnosis Tool for CMOS VLSI Chips. DAC 1996: 548-551 | |
| c1 | Chin-Chi Teng, Yi-Kan Cheng, Elyse Rosenbaum, Sung-Mo Kang: Hierarchical Electromigration Reliability Diagnosis for VLSI Interconnects. DAC 1996: 752-757 | |
| 1993 | ||
| j1 | Robert H. Tu, Elyse Rosenbaum, Wilson Y. Chan, Chester C. Li, Eric Minami, Khandker Quader, Ping K. Ko, Chenming Hu: Berkeley reliability tools-BERT. IEEE Trans. on CAD of Integrated Circuits and Systems 12(10): 1524-1534 (1993) | |
Colors in the list of coauthors
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