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 | 1997 | |
|---|---|---|
| j2 |      | Srimat T. Chakradhar, Steven G. Rothweiler, Vishwani D. Agrawal: Redundancy removal and test generation for circuits with non-Boolean primitives. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1370-1377 (1997) |
| c6 | | Srimat T. Chakradhar, Vijay Gangaram, Steven G. Rothweiler: Deriving Signal Constraints to Accelerate Sequential Test Generation. VLSI Design 1997: 488-494 |
| 1995 | ||
| c5 | | Srimat T. Chakradhar, Steven G. Rothweiler: Redundancy Removal and Test Generation for Circuits with Non-Boolean Primitives. VTS 1995: 12-19 |
| 1993 | ||
| j1 | | Srimat T. Chakradhar, Vishwani D. Agrawal, Steven G. Rothweiler: A transitive closure algorithm for test generation. IEEE Trans. on CAD of Integrated Circuits and Systems 12(7): 1015-1028 (1993) |
| c4 | | Srimat T. Chakradhar, Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler: Sequential Circuit Delay optimization Using Global Path Delays. DAC 1993: 483-489 |
| 1992 | ||
| c3 | | Sujit Dey, Miodrag Potkonjak, Steven G. Rothweiler: Performance optimization of sequential circuits by eliminating retiming bottlenecks. ICCAD 1992: 504-509 |
| 1988 | ||
| c2 | | Ruey-Sing Wei, Steven G. Rothweiler, Jing-Yang Jou: BECOME: Behavior Level Circuit Synthesis Based on Structure Mapping. DAC 1988: 409-414 |
| c1 | | Chia-Jeng Tseng, Ruey-Sing Wei, Steven G. Rothweiler, Michael M. Tong, Ajoy K. Bose: Bridge: A Versatile Behavioral Synthesis System. DAC 1988: 415-420 |
| 1 | Vishwani D. Agrawal | |
| 2 | Ajoy K. Bose | |
| 3 | Srimat T. Chakradhar | |
| 4 | Sujit Dey | |
| 5 | Vijay Gangaram | |
| 6 | Jing-Yang Jou | |
| 7 | Miodrag Potkonjak | |
| 8 | Michael M. Tong | |
| 9 | Chia-Jeng Tseng | |
| 10 | Ruey-Sing Wei |
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