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 | 2013 | |
|---|---|---|
| j10 |      | Amitabh Das, Jean DaRolt, Santosh Ghosh, Stefaan Seys, Sophie Dupuis, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede: Secure JTAG Implementation Using Schnorr Protocol. J. Electronic Testing 29(2): 193-209 (2013) |
| 2012 | ||
| j9 | | Jean DaRolt, Amitabh Das, Santosh Ghosh, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede: Scan attacks on side-channel and fault attack resistant public-key implementations. J. Cryptographic Engineering 2(4): 207-219 (2012) |
| j8 | | R. Possamai Bastos, F. Sill Torres, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: Novel transient-fault detection circuit featuring enhanced bulk built-in current sensor with low-power sleep-mode. Microelectronics Reliability 52(9-10): 1781-1786 (2012) |
| c43 | | Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede: A New Scan Attack on RSA in Presence of Industrial Countermeasures. COSADE 2012: 89-104 |
| c42 | | Jean DaRolt, Amitabh Das, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Ingrid Verbauwhede: A scan-based attack on Elliptic Curve Cryptosystems in presence of industrial Design-for-Testability structures. DFT 2012: 43-48 |
| c41 | | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: On-chip test comparison for protecting confidential data in secure ICs. European Test Symposium 2012: 1 |
| c40 | | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: Are advanced DfT structures sufficient for preventing scan-attacks? VTS 2012: 246-251 |
| 2011 | ||
| c39 | | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre, Miroslav Valka, Denis Réal: Power consumption traces realignment to improve differential power analysis. DDECS 2011: 201-206 |
| c38 | | Rodrigo P. Bastos, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: A New Bulk Built-In Current Sensor-Based Strategy for Dealing with Long-Duration Transient Faults in Deep-Submicron Technologies. DFT 2011: 302-308 |
| c37 | | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: Scan Attacks and Countermeasures in Presence of Scan Response Compactors. European Test Symposium 2011: 19-24 |
| c36 | | Jean DaRolt, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: New security threats against chips containing scan chain structures. HOST 2011: 110 |
| 2010 | ||
| j7 | | Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre: Self-Test Techniques for Crypto-Devices. IEEE Trans. VLSI Syst. 18(2): 329-333 (2010) |
| c35 | | Jerome Di-Battista, Jean-Christophe Courrège, Bruno Rouzeyre, Lionel Torres, Philippe Perdu: When Failure Analysis Meets Side-Channel Attacks. CHES 2010: 188-202 |
| c34 | | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: Ensuring high testability without degrading security: Embedded tutorial on "test and security". DDECS 2010: 6 |
| c33 | | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: Evaluation of Resistance to Differential Power Analysis: Execution Time Optimizations for Designers. DELTA 2010: 256-261 |
| c32 | | K. Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: Evaluation of concurrent error detection techniques on the Advanced Encryption Standard. European Test Symposium 2010: 252 |
| c31 | | K. Bousselam, Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: Evaluation of concurrent error detection techniques on the advanced encryption standard. IOLTS 2010: 223-228 |
| 2009 | ||
| j6 | | Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre: A Reliable Architecture for Parallel Implementations of the Advanced Encryption Standard. J. Electronic Testing 25(4-5): 269-278 (2009) |
| 2008 | ||
| c30 | | M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre: AES-Based BIST: Self-Test, Test Pattern Generation and Signature Analysis. DELTA 2008: 314-321 |
| c29 | | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: An Integrated Validation Environment for Differential Power Analysis. DELTA 2008: 527-532 |
| c28 | | Giorgio Di Natale, M. Doulcier, Marie-Lise Flottes, Bruno Rouzeyre: A Reliable Architecture for the Advanced Encryption Standard. European Test Symposium 2008: 13-18 |
| c27 | | Julien Dalmasso, Érika F. Cota, Marie-Lise Flottes, Bruno Rouzeyre: Improving the Test of NoC-Based SoCs with Help of Compression Schemes. ISVLSI 2008: 139-144 |
| 2007 | ||
| j5 | | David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: Securing Scan Control in Crypto Chips. J. Electronic Testing 23(5): 457-464 (2007) |
| c26 |  | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: A Novel Parity Bit Scheme for SBox in AES Circuits. DDECS 2007: 267-271 |
| c25 | | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: An On-Line Fault Detection Scheme for SBoxes in Secure Circuits. IOLTS 2007: 57-62 |
| c24 | | Giorgio Di Natale, Marie-Lise Flottes, Bruno Rouzeyre: A Dependable Parallel Architecture for SBoxes. ReCoSoC 2007: 132-137 |
| c23 | | Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Test data compression and TAM design. VLSI-SoC 2007: 178-183 |
| i1 | | Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre: Mutation Sampling Technique for the Generation of Structural Test Data. CoRR abs/0710.4802 (2007) |
| 2006 | ||
| c22 | | David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: A secure scan design methodology. DATE 2006: 1177-1178 |
| c21 | | Julien Dalmasso, Marie-Lise Flottes, Bruno Rouzeyre: Fitting ATE Channels with Scan Chains: a Comparison between a Test Data Compression Technique and Serial Loading of Scan Chains. DELTA 2006: 295-300 |
| c20 | | David Hély, Frédéric Bancel, Marie-Lise Flottes, Bruno Rouzeyre: Secure Scan Techniques: A Comparison. IOLTS 2006: 119-124 |
| 2005 | ||
| c19 | | Mathieu Scholivé, Vincent Beroulle, Chantal Robach, Marie-Lise Flottes, Bruno Rouzeyre: Mutation Sampling Technique for the Generation of Structural Test Data. DATE 2005: 1022-1023 |
| 2004 | ||
| j4 | | Solaiman Rahim, Bruno Rouzeyre, Lionel Torres: A Flip-Flop Matching Engine to Verify Sequential Optimizations. Computers and Artificial Intelligence 23(5): 437-460 (2004) |
| c18 | | Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre: An Arithmetic Structure for Test Data Horizontal Compression. DATE 2004: 428-435 |
| c17 | | Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre: On Using Test Vector Differences for Reducing Test Pin Numbers. DELTA 2004: 275-280 |
| c16 | | David Hély, Marie-Lise Flottes, Frédéric Bancel, Bruno Rouzeyre, Nicolas Bérard, Michel Renovell: Scan Design and Secure Chip. IOLTS 2004: 219-226 |
| 2003 | ||
| c15 | | Solaiman Rahim, Bruno Rouzeyre, Lionel Torres, Jérôme Rampon: Matching in the presence of don't cares and redundant sequential elements for sequential equivalence checking. HLDVT 2003: 129-134 |
| 2002 | ||
| c14 | | Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre: Taylor Expansion Diagrams: A Compact, Canonical Representation with Applications to Symbolic Verification. DATE 2002: 285-289 |
| c13 | | Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre: A Heuristic for Test Scheduling at System Level. DATE 2002: 1124 |
| c12 | | Marie-Lise Flottes, Regis Poirier, Bruno Rouzeyre: A simple and effective compression scheme for test pins reduction. HLDVT 2002: 165-168 |
| e1 | | Michel Robert, Bruno Rouzeyre, Christian Piguet, Marie-Lise Flottes (Eds.): SOC Design Methodologies, IFIP TC10/WG10.5 Eleventh International Conference on Very Large Scale Integration of Systems-on/Chip (VLSI-SOC'01), December 3-5, 2001, Montpellier, France. IFIP Conference Proceedings 218, Kluwer 2002, isbn 1-4020-7148-5 |
| 2001 | ||
| j3 | | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre: A Method for Trading off Test Time, Area and Fault Coverage in Datapath BIST Synthesis. J. Electronic Testing 17(3-4): 331-339 (2001) |
| c11 | | Maciej J. Ciesielski, Priyank Kalla, Zhihong Zeng, Bruno Rouzeyre: Taylor expansion diagrams: a new representation for RTL verification. HLDVT 2001: 70-75 |
| c10 | | Zhihong Zeng, Maciej J. Ciesielski, Bruno Rouzeyre: Functional Test Generation using Constraint Logic Programming. VLSI-SOC 2001: 375-387 |
| c9 | | Marie-Lise Flottes, Julien Pouget, Bruno Rouzeyre: Power-Constrained Test Scheduling for SoCs Under a "no session" Scheme. VLSI-SOC 2001: 401-412 |
| 2000 | ||
| c8 | | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre: BISTing data paths at behavioral level. ITC 2000: 672-680 |
| 1999 | ||
| j2 | | David Berthelot, Marie-Lise Flottes, Bruno Rouzeyre: BISTing Datapaths under Heterogeneous Test Schemes. J. Electronic Testing 14(1-2): 115-123 (1999) |
| 1998 | ||
| c7 | | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre: Alleviating DFT Cost Using Testability Driven HLS. Asian Test Symposium 1998: 46-51 |
| c6 | | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe: Scanning Datapaths: A Fast and Effective Partial Scan Selection Technique. DATE 1998: 921-922 |
| c5 | | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre, L. Volpe: Low Cost Partial Scan Design: A High Level Synthesis Approach. VTS 1998: 332-340 |
| 1997 | ||
| j1 | | Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre: Improving Testability of Non-Scan Designs during Behavioral Synthesis. J. Electronic Testing 11(1): 29-42 (1997) |
| c4 | | Marie-Lise Flottes, R. Pires, Bruno Rouzeyre: Analyzing testability from behavioral to RT level. ED&TC 1997: 158-165 |
| 1995 | ||
| c3 | | Christian Landrault, Marie-Lise Flottes, Bruno Rouzeyre: Is High-Level Test Synthesis Just Design for Test? ITC 1995: 294 |
| 1994 | ||
| c2 | | Bruno Rouzeyre, D. Dupont, G. Sagnes: Component Selection, Scheduling and Control Schemes for High Level Synthesis. EDAC-ETC-EUROASIC 1994: 482-489 |
| c1 | | Marie-Lise Flottes, D. Hammad, Bruno Rouzeyre: Automatic Synthesis of BISTed Data Paths From High Level Specification. EDAC-ETC-EUROASIC 1994: 591-598 |
Colors in the list of coauthors
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