Vyacheslav Rovner

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	2010
j1		Tejas Jhaveri, Vyacheslav Rovner, Lars Liebmann, Larry T. Pileggi, Andrzej J. Strojwas, Jason Hibbeler: Co-Optimization of Circuits, Layout and Lithography for Predictive Technology Scaling Beyond Gratings. IEEE Trans. on CAD of Integrated Circuits and Systems 29(4): 509-527 (2010)
	2009
c4		Andrzej J. Strojwas, Tejas Jhaveri, Vyacheslav Rovner, Lawrence T. Pileggi: Creating an affordable 22nm node using design-lithography co-optimization. DAC 2009: 95-96
	2005
c3		V. Kheterpal, Vyacheslav Rovner, T. G. Hersan, D. Motiani, Y. Takegawa, Andrzej J. Strojwas, Lawrence T. Pileggi: Design methodology for IC manufacturability based on regular logic-bricks. DAC 2005: 353-358
	2004
c2		Thomas J. Vogels, Thomas Zanon, Rao Desineni, R. D. (Shawn) Blanton, Wojciech Maly, Jason G. Brown, Jeffrey E. Nelson, Y. Fei, X. Huang, Padmini Gopalakrishnan, Mahim Mishra, Vyacheslav Rovner, S. Tiwary: Benchmarking Diagnosis Algorithms With a Diverse Set of IC Deformations. ITC 2004: 508-517
	2003
c1		Lawrence T. Pileggi, Herman Schmit, Andrzej J. Strojwas, Padmini Gopalakrishnan, V. Kheterpal, Aneesh Koorapaty, Chetan Patel, Vyacheslav Rovner, K. Y. Tong: Exploring regular fabrics to optimize the performance-cost trade-off. DAC 2003: 782-787

Coauthor Index

1	R. D. (Shawn) Blanton (Ronald D. Blanton)	[c2]
2	Jason G. Brown	[c2]
3	Rao Desineni	[c2]
4	Y. Fei	[c2]
5	Padmini Gopalakrishnan	[c2] [c1]
6	T. G. Hersan	[c3]
7	Jason Hibbeler	[j1]
8	X. Huang	[c2]
9	Tejas Jhaveri	[j1] [c4]
10	V. Kheterpal	[c3] [c1]
11	Aneesh Koorapaty	[c1]
12	Lars Liebmann	[j1]
13	Wojciech Maly	[c2]
14	Mahim Mishra	[c2]
15	D. Motiani	[c3]
16	Jeffrey E. Nelson	[c2]
17	Chetan Patel	[c1]
18	Lawrence T. Pileggi (Larry T. Pileggi, Lawrence T. Pillage)	[j1] [c4] [c3] [c1]
19	Herman Schmit	[c1]
20	Andrzej J. Strojwas (Andreas J. Strojwas)	[j1] [c4] [c3] [c1]
21	Y. Takegawa	[c3]
22	S. Tiwary	[c2]
23	K. Y. Tong	[c1]
24	Thomas J. Vogels	[c2]
25	Thomas Zanon	[c2]

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