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 | 2013 | |
|---|---|---|
| j10 |      | Koushik Chakraborty, Sanghamitra Roy: Architecturally Homogeneous Power-Performance Heterogeneous Multicore Systems. IEEE Trans. VLSI Syst. 21(4): 670-679 (2013) |
| c24 | | Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy: Proactive aging management in heterogeneous NoCs through a criticality-driven routing approach. DATE 2013: 1032-1037 |
| 2012 | ||
| j9 | | Saurabh Kothawade, Koushik Chakraborty, Sanghamitra Roy, Yiding Han: Analysis of intermittent timing fault vulnerability. Microelectronics Reliability 52(7): 1515-1522 (2012) |
| j8 | | Koushik Chakraborty, Sanghamitra Roy: Stack Aware Threshold Voltage Assignment in 3-D Multicore Designs. IEEE Trans. VLSI Syst. 20(3): 512-522 (2012) |
| c23 | | Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy: Towards graceful aging degradation in NoCs through an adaptive routing algorithm. DAC 2012: 382-391 |
| c22 | | Sanghamitra Roy, Koushik Chakraborty: Predicting timing violations through instruction-level path sensitization analysis. DAC 2012: 1074-1081 |
| c21 | | Kshitij Bhardwaj, Koushik Chakraborty, Sanghamitra Roy: An MILP-based aging-aware routing algorithm for NoCs. DATE 2012: 326-331 |
| c20 | | Saurabh Kothawade, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy: Mitigating NBTI in the physical register file through stress prediction. ICCD 2012: 345-351 |
| c19 | | Yiding Han, Koushik Chakraborty, Sanghamitra Roy: DOC: Fast and accurate congestion analysis for global routing. ICCD 2012: 508-509 |
| c18 | | Jason Allred, Sanghamitra Roy, Koushik Chakraborty: Designing for dark silicon: a methodological perspective on energy efficient systems. ISLPED 2012: 255-260 |
| c17 | | Satyajit Desai, Sanghamitra Roy, Koushik Chakraborty: Process variation aware DRAM design using block based adaptive body biasing algorithm. ISQED 2012: 255-261 |
| c16 | | Kshitij Bhardwaj, Sanghamitra Roy, Koushik Chakraborty: Power-Performance Yield optimization for MPSoCs using MILP. ISQED 2012: 764-771 |
| 2011 | ||
| j7 | | Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty: Microprocessor Power Supply Noise Aware Floorplanning Using a Circuit-Architectural Framework. J. Low Power Electronics 7(3): 303-313 (2011) |
| j6 | | Sanghamitra Roy, Koushik Chakraborty: Exploiting dynamic micro-architecture usage in gate sizing. Microprocessors and Microsystems - Embedded Hardware Design 35(4): 417-425 (2011) |
| j5 | | Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala: Design and Implementation of a Throughput-Optimized GPU Floorplanning Algorithm. ACM Trans. Design Autom. Electr. Syst. 16(3): 23 (2011) |
| c15 | | Koushik Chakraborty, Sanghamitra Roy: Topologically homogeneous power-performance heterogeneous multicore systems. DATE 2011: 125-130 |
| c14 | | Yiding Han, Dean Michael Ancajas, Koushik Chakraborty, Sanghamitra Roy: Exploring high throughput computing paradigm for global routing. ICCAD 2011: 298-305 |
| c13 | | Saurabh Kothawade, Koushik Chakraborty, Sanghamitra Roy: Analysis and mitigation of NBTI aging in register file: An end-to-end approach. ISQED 2011: 1-7 |
| c12 | | Mandar Padmawar, Sanghamitra Roy, Koushik Chakraborty: Integrated circuit-architectural framework for PSN aware floorplanning in microprocessors. ISQED 2011: 212-218 |
| c11 | | Yiding Han, Sanghamitra Roy, Koushik Chakraborty: Optimizing simulated annealing on GPU: A case study with IC floorplanning. ISQED 2011: 263-269 |
| c10 | | Yiding Han, Koushik Chakraborty, Sanghamitra Roy, Vilasita Kuntamukkala: A GPU Algorithm for IC Floorplanning: Specification, Analysis and Optimization. VLSI Design 2011: 159-164 |
| 2010 | ||
| j4 | | Koushik Chakraborty, Sanghamitra Roy: A Novel Threshold Voltage Assignment for 3D Multicore Designs. J. Low Power Electronics 6(3): 436-446 (2010) |
| c9 | | Sanghamitra Roy, Koushik Chakraborty: Microarchitecture aware gate sizing: A framework for circuit-architecture co-optimization. ICCD 2010: 222-228 |
| c8 | | Sanghamitra Roy, Koushik Chakraborty: A convex optimization framework for leakage aware thermal provisioning in 3D multicore architectures. ISQED 2010: 804-811 |
| c7 | | Koushik Chakraborty, Sanghamitra Roy: Rethinking Threshold Voltage Assignment in 3D Multicore Designs. VLSI Design 2010: 375-380 |
| 2008 | ||
| c6 | | Sanghamitra Roy, Yu Hen Hu, Charlie Chung-Ping Chen, Shih-Pin Hung, Tse-Yu Chiang, Jiuan-Guei Tseng: An optimal algorithm for sizing sequential circuits for industrial library based designs. ASP-DAC 2008: 148-151 |
| 2007 | ||
| j3 | | Sanghamitra Roy, Weijen Chen, Charlie Chung-Ping Chen, Yu Hen Hu: Numerically Convex Forms and Their Application in Gate Sizing. IEEE Trans. on CAD of Integrated Circuits and Systems 26(9): 1637-1647 (2007) |
| c5 | | Sanghamitra Roy, Charlie Chung-Ping Chen: SmartSmooth: A linear time convexity preserving smoothing algorithm for numerically convex data with application to VLSI design. ASP-DAC 2007: 559-564 |
| 2006 | ||
| c4 | | Sanghamitra Roy, Charlie Chung-Ping Chen: ConvexSmooth: A simultaneous convex fitting and smoothing algorithm for convex optimization problems. ISQED 2006: 665-670 |
| 2005 | ||
| j2 | | Sanghamitra Roy, Prith Banerjee: An Algorithm for Trading Off Quantization Error with Hardware Resources for MATLAB-Based FPGA Design. IEEE Trans. Computers 54(7): 886-896 (2005) |
| c3 |  | Sanghamitra Roy, Weijen Chen: ConvexFit: an optimal minimum-error convex fitting and smoothing algorithm with application to gate-sizing. ICCAD 2005: 196-203 |
| 2004 | ||
| c2 | | Sanghamitra Roy, Prithviraj Banerjee: An algorithm for converting floating-point computations to fixed-point in MATLAB based FPGA design. DAC 2004: 484-487 |
| c1 | | Sanghamitra Roy, Debjit Sinha, Prithviraj Banerjee: An algorithm for trading off quantization error with hardware resources for MATLAB based FPGA design. FPGA 2004: 256 |
| 2003 | ||
| j1 | | Biswajit Sarkar, Sanghamitra Roy, Debranjan Sarkar: Hierarchical representation of digitized curves through dominant point detection. Pattern Recognition Letters 24(15): 2869-2882 (2003) |
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