Joe D. Rutledge

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	1987
j1		Zeev Barzilai, J. Lawrence Carter, Barry K. Rosen, Joe D. Rutledge: HSS--A High-Speed Simulator. IEEE Trans. on CAD of Integrated Circuits and Systems 6(4): 601-617 (1987)
	1986
c1		Zeev Barzilai, J. Lawrence Carter, Vijay S. Iyengar, Indira Nair, Barry K. Rosen, Joe D. Rutledge, Gabriel M. Silberman: Efficient Fault Simulation of CMOS Circuits with Accurate Models. ITC 1986: 520-529

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