F. Jesús Sánchez

Indu Bhagat, Enric Gibert, F. Jesús Sánchez, Antonio González: Global productiveness propagation: a code optimization technique to speculatively prune useless narrow computations. LCTES 2011: 161-170

Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli: AGAMOS: A Graph-Based Approach to Modulo Scheduling for Clustered Microarchitectures. IEEE Trans. Computers 58(6): 770-783 (2009)

Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen, Hong Wang, John Paul Shen: Mitosis: A Speculative Multithreaded Processor Based on Precomputation Slices. IEEE Trans. Parallel Distrib. Syst. 19(7): 914-925 (2008)

Josep M. Codina, F. Jesús Sánchez, Antonio González: Virtual Cluster Scheduling Through the Scheduling Graph. CGO 2007: 89-101

Enric Gibert, F. Jesús Sánchez, Antonio González: Instruction scheduling for a clustered VLIW processor with a word-interleaved cache. Concurrency and Computation: Practice and Experience 18(11): 1391-1411 (2006)

Enric Gibert, F. Jesús Sánchez, Antonio González: Distributed Data Cache Designs for Clustered VLIW Processors. IEEE Trans. Computers 54(10): 1227-1241 (2005)

Enric Gibert, Jaume Abella, F. Jesús Sánchez, Xavier Vera, Antonio González: Variable-Based Multi-module Data Caches for Clustered VLIW Processors. IEEE PACT 2005: 207-217

Carlos Madriles, Carlos García Quiñones, F. Jesús Sánchez, Pedro Marcuello, Antonio González: The Mitosis Speculative Multithreaded Architectures. PARCO 2005: 27-40

Carlos García Quiñones, Carlos Madriles, F. Jesús Sánchez, Pedro Marcuello, Antonio González, Dean M. Tullsen: Mitosis compiler: an infrastructure for speculative threading based on pre-computation slices. PLDI 2005: 269-279

Enric Gibert, F. Jesús Sánchez, Antonio González: Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache. CGO 2003: 193-203

Enric Gibert, F. Jesús Sánchez, Antonio González: Flexible Compiler-Managed L0 Buffers for Clustered VLIW Processors. MICRO 2003: 315-325

Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González, David R. Kaeli: Exploiting Pseudo-Schedules to Guide Data Dependence Graph Partitioning. IEEE PACT 2002: 281-290

Enric Gibert, F. Jesús Sánchez, Antonio González: An interleaved cache clustered VLIW processor. ICS 2002: 210-219

Enric Gibert, F. Jesús Sánchez, Antonio González: Effective instruction scheduling techniques for an interleaved cache clustered VLIW processor. MICRO 2002: 123-133

F. Jesús Sánchez, Antonio González: Clustered Modulo Scheduling in a VLIW Architecture with Distributed Cache . J. Instruction-Level Parallelism 3 (2001)

Josep M. Codina, F. Jesús Sánchez, Antonio González: A Unified Modulo Scheduling and Register Allocation Technique for Clustered Processors. IEEE PACT 2001: 175-184

Alex Aletà, Josep M. Codina, F. Jesús Sánchez, Antonio González: Graph-partitioning based instruction scheduling for clustered processors. MICRO 2001: 150-159

F. Jesús Sánchez, Antonio González: Analyzing Data Locality in Numeric Applications. IEEE Micro 20(4): 58-66 (2000)

F. Jesús Sánchez, Antonio González: The Effectiveness of Loop Unrolling for Modulo Scheduling in Clustered VLIW Architectures. ICPP 2000: 555-

F. Jesús Sánchez, Antonio González: Instruction Scheduling for Clustered VLIW Architectures. ISSS 2000: 41-46

F. Jesús Sánchez, Antonio González: Modulo scheduling for a fully-distributed clustered VLIW architecture. MICRO 2000: 124-133

F. Jesús Sánchez, Antonio González: Software Data Prefetching for Software Pipelined Loops. J. Parallel Distrib. Comput. 58(2): 236-259 (1999)

F. Jesús Sánchez, Antonio González: A locality sensitive multi-module cache with explicit management. International Conference on Supercomputing 1999: 51-59

F. Jesús Sánchez, Antonio González: Fast, Accurate and Flexible Data Locality Analysis. IEEE PACT 1998: 124-129

F. Jesús Sánchez, Antonio González, Mateo Valero: Static Locality Analysis for Cache Management. IEEE PACT 1997: 261-271

F. Jesús Sánchez, Antonio González: Cache Sensitive Modulo Scheduling. MICRO 1997: 338-348