Shuichi Sakai

Ryota Shioya, Naruki Kurata, Takashi Toyoshima, Masahiro Goshima, Shuichi Sakai: Register Indirect Jump Target Forwarding. IEICE Transactions 96-D(2): 278-288 (2013)

Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai: Low-Overhead Architecture for Security Tag. IEICE Transactions 94-D(1): 69-78 (2011)

Ryota Shioya, Kazuo Horio, Masahiro Goshima, Shuichi Sakai: Register Cache System Not for Latency Reduction Purpose. MICRO 2010: 301-312

Shuichi Sakai, Hidetoshi Onodera, Hiroto Yasuura, James C. Hoe: Dependable VLSI: device, design and architecture: how should they cooperate? ASP-DAC 2009: 859-860

Ryota Shioya, Daewung Kim, Kazuo Horio, Masahiro Goshima, Shuichi Sakai: Low-Overhead Architecture for Security Tag. PRDC 2009: 135-142

Kunbo Li, Ryota Shioya, Masahiro Goshima, Shuichi Sakai: String-Wise Information Flow Tracking against Script Injection Attacks. PRDC 2009: 169-176

Shuichi Sakai, Masahiro Goshima, Hidetsugu Irie: Ultra Dependable Processor. IEICE Transactions 91-C(9): 1386-1393 (2008)

Tomoyoshi Kinoshita, Ibuki Handa, Makoto Muto, Shuichi Sakai, Hidehiko Tanaka: Musical part separation based on perceptual hierarchy. Systems and Computers in Japan 38(2): 91-100 (2007)

Hidetsugu Irie, Ken Sugimoto, Masahiro Goshima, Shuichi Sakai: Preventing timing errors on register writes: mechanisms of detections and recoveries. SIGARCH Computer Architecture News 35(5): 25-31 (2007)

Luong Dinh Hung, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai: Utilization of SECDED for soft error and variation-induced defect tolerance in caches. DATE 2007: 1134-1139

Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai: SEVA: A Soft-Error- and Variation-Aware Cache Architecture. PRDC 2006: 47-54

Satoshi Katsunuma, Hiroyuki Kurita, Ryota Shioya, Kazuto Shimizu, Hidetsugu Irie, Masahiro Goshima, Shuichi Sakai: Base Address Recognition with Data Flow Tracking for Injection Attack Detection. PRDC 2006: 165-172

Koichi Miura, Motomu Takano, Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka: Associating semantically structured cooking videos with their preparation steps. Systems and Computers in Japan 36(2): 51-62 (2005)

Luong Dinh Hung, Masahiro Goshima, Shuichi Sakai: Mitigating Soft Errors in Highly Associative Cache with CAM-based Tag. ICCD 2005: 342-350

Luong Dinh Hung, Shuichi Sakai: Dynamic Estimation of Task Level Parallelism with Operating System Support. ISPAN 2005: 358-363

Reiko Hamada, Jun Okabe, Ichiro Ide, Shin'ichi Satoh, Shuichi Sakai, Hidehiko Tanaka: Cooking navi: assistant for daily cooking in kitchen. ACM Multimedia 2005: 371-374

Reiko Hamada, Koichi Miura, Ichiro Ide, Shin'ichi Satoh, Shuichi Sakai, Hidehiko Tanaka: Multimedia Integration for Cooking Video Indexing. PCM (2) 2004: 657-664

Shuichi Sakai, Mitsunori Togasaki, Koichi Yamazaki: A note on greedy algorithms for the maximum weighted independent set problem. Discrete Applied Mathematics 126(2-3): 313-322 (2003)

Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka: Compilation of dictionaries for semantic attribute analysis of television news captions. Systems and Computers in Japan 34(12): 32-44 (2003)

Koichi Miura, Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka: Associating Cooking Video Segments with Preparation Steps. CIVR 2003: 174-183

Hideyuki Miura, Luong Dinh Hung, Chitaka Iwama, Daisuke Tashiro, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka: Compiler-Assisted Thread Level Control Speculation. Euro-Par 2003: 603-608

Yoshimitsu Yanagawa, Luong Dinh Hung, Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka: Complexity Analysis of a Cache Controller for Speculative Multithreading Chip Multiprocessors. HiPC 2003: 393-404

Okihisa Utsumi, Koichi Miura, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka: An object detection method for describing soccer games from video. ICME (1) 2002: 45-48

Shuichi Sakai: CMP on SoC: Architect's View. ISSS 2002: 101-102

Chitaka Iwama, Niko Demus Barli, Shuichi Sakai, Hidehiko Tanaka: Improving Conditional Branch Prediction on Speculative Multithreading Architectures. Euro-Par 2001: 413-417

Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka: Structural analysis of cooking preparation steps in Japanese. IRAL 2000: 157-164

Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka: Scene identification in news video by character region segmentation. ACM Multimedia Workshops 2000: 195-200

Reiko Hamada, Ichiro Ide, Shuichi Sakai: Associating cooking video with related textbook. ACM Multimedia Workshops 2000: 237-241

Antonio Magnaghi, Shuichi Sakai, Hidehiko Tanaka: Inter-procedural Analysis for Parallelization of Java Programs. ACPC 1999: 594-595

Ichiro Ide, Reiko Hamada, Shuichi Sakai, Hidehiko Tanaka: Relating Graphical Features with Concept Classes for Automatic News Video Indexing. Intelligent Information Integration 1999

Reiko Hamada, Ichiro Ide, Shuichi Sakai, Hidehiko Tanaka: Associating video with related documents. ACM Multimedia (2) 1999: 17-20

Masaaki Honda, Takeo Igarashi, Hidehiko Tanaka, Shuichi Sakai: Integrated Manipulation: Context-Aware Manipulation of 2D Diagrams. ACM Symposium on User Interface Software and Technology 1999: 159-160

Yuetsu Kodama, Hirofumi Sakane, Hanpei Koike, Mitsuhisa Sato, Shuichi Sakai, Yoshinori Yamaguchi: Parallel Execution of Radix Sort Program Using Fine-Grain Communication. IEEE PACT 1997: 136-145

Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi: Experience with Fine-Grain Communication in EM-X Multiprocessor for Parallel Sparse Matrix Computation. IPPS 1997: 242-248

Andrew Sohn, Yuetsu Kodama, Jui Ku, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi: Fine-Grain Multithreading with the EM-X Multiprocessor. SPAA 1997: 189-198

Kazuaki Okamoto, Shuichi Sakai, Hiroshi Matsuoka, Takashi Yokota, Hideo Hirono: Multithread execution mechanisms on RICA-1 for massively parallel computation. IEEE PACT 1996: 116-121

Andrew Sohn, Jui Ku, Yuetsu Kodama, Mitsuhisa Sato, Hirofumi Sakane, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi: Identifying the capability of overlapping computation with communication. IEEE PACT 1996: 133-138

Shuichi Sakai, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hiroshi Matsuoka, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota: Reduced Interprocessor-Communication Architecture and its Implementation on EM-4. Parallel Computing 21(5): 753-769 (1995)

Hayato Yamana, Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi: A Macrotask-level Unlimited Speculative Execution on Multiprocessors. International Conference on Supercomputing 1995: 328-337

Yuetsu Kodama, Hirohumi Sakane, Mitsuhisa Sato, Hayato Yamana, Shuichi Sakai, Yoshinori Yamaguchi: The EM-X Parallel Computer: Architecture and Basic Performance. ISCA 1995: 14-23

Atsushi Hori, Takashi Yokota, Yutaka Ishikawa, Shuichi Sakai, Hiroki Konaka, Munenori Maeda, Takashi Tomokiyo, Jörg Nolte, Hiroshi Matsuoka, Kazuaki Okamoto, Hideo Hirono: Time Space Sharing Scheduling and Architectural Support. JSSPP 1995: 92-105

Shuichi Sakai: Overview of RWC Massively Parallel Computer Project. HPDC 1994: 5

Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi: EM-C: Programming with Explicit Parallelism and Locality for EM-4 Multiprocessor. IFIP PACT 1994: 3-14

Mitsuhisa Sato, Yuetsu Kodama, Yoshinori Yamaguchi, Shuichi Sakai: Experience with Executing Shared Memory Programs using Fine-Grain Communication and Multithreading in EM-4. IPPS 1994: 630-636

Andrew Sohn, Mitsuhisa Sato, Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi: Nonnumeric search results on the EM-4 distributed-memory multiprocessor. SC 1994: 301-310

Mitsuhisa Sato, Yuetsu Kodama, Hirofumi Sakane, Yoshinori Yamaguchi, Shuichi Sakai: Programming with Distributed Data Structure for EM-X Multiprocessor. Theory and Practice of Parallel Programming 1994: 472-483

Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi: Design and Implementation of a Circular Omega Network in the EM-4. Parallel Computing 19(2): 125-142 (1993)

Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi: Evaluation of parallel execution performance by highly parallel computer EM-4. Systems and Computers in Japan 24(9): 32-41 (1993)

Yuetsu Kodama, Yasuhito Koumura, Mitsuhisa Sato, Hirohumi Sakane, Shuichi Sakai, Yoshinori Yamaguchi: EMC-Y: Parallel Processing Element Optimizing Communication and Computation. International Conference on Supercomputing 1993: 167-174

Shuichi Sakai, Kazuaki Okamoto, Hiroshi Matsuoka, Hideo Hirono, Yuetsu Kodama, Mitsuhisa Sato: Super-Threading: Architectural and Software Mechanisms for Optimizing Parallel Computation. International Conference on Supercomputing 1993: 251-260

Shuichi Sakai, Hiroshi Matsuoka, Yuetsu Kodama, Mitsuhisa Sato, Andrew Shaw, Hideo Hirono, Kazuaki Okamoto, Takashi Yokota: RICA: Reduced Interprocessor-Communication Architecture - Concept and Mechanisms. SPDP 1993: 122-127

Kazuaki Okamoto, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi: Methodologies in development and testing of the dataflow machine EM-4. Parallel Computing 18(8): 901-912 (1992)

Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi: Evaluation of the EM-4 Highly Parallel Computer using a Game Tree Searching Problem. FGCS 1992: 731-738

Mitsuhisa Sato, Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi, Yasuhito Koumura: Thread-based Programming for the EM-4 Hybrid Dataflow Machine. ISCA 1992: 146-155

Kenji Toda, Kenji Nishida, Shuichi Sakai, Toshio Shimada: A priority forwarding scheme for real-time multistage interconnection networks. RTSS 1992: 208-217

Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi: Design and Implementation of a Versatile Interconnection Network in the EM-4. ICPP (1) 1991: 426-430

Shuichi Sakai, Yuetsu Kodama, Yoshinori Yamaguchi: Prototype Implementation of a Highly Parallel Dataflow Machine EM-4. IPPS 1991: 278-286

Kenji Toda, Kenji Nishida, Yoshinobu Uchibori, Shuichi Sakai, Toshio Shimada: Parallel Multi-Context Architecture with High-Speed Synchronization Mechanism. IPPS 1991: 336-343

Yuetsu Kodama, Shuichi Sakai, Yoshinori Yamaguchi: Load balancing by function distribution on the EM-4 prototype. SC 1991: 522-531

Toshitsugu Yuba, Toshio Shimada, Yoshinori Yamaguchi, Kei Hiraki, Shuichi Sakai: Dataflow computer development in Japan. ICS 1990: 140-147

Yoshinori Yamaguchi, Shuichi Sakai, Kei Hiraki, Yuetsu Kodama: An Architectural Disgn of a Highly Parallel Dataflow Machine. IFIP Congress 1989: 1155-1160

Shuichi Sakai, Yoshinori Yamaguchi, Kei Hiraki, Yuetsu Kodama, Toshitsugu Yuba: An Architecture of a Dataflow Single Chip Processor. ISCA 1989: 46-53