- CSB - MetaPress - Google - Bing - Yahoo
 | 2013 | |
|---|---|---|
| j47 |      | Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Hiroshi Toshiyoshi, Makoto Takamiya, Takao Someya, Takayasu Sakurai: Insole Pedometer With Piezoelectric Energy Harvester and 2 V Organic Circuits. J. Solid-State Circuits 48(1): 255-264 (2013) |
| j46 | | Shinji Miyano, Shinichi Moriwaki, Yasue Yamamoto, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Hirofumi Shinohara: Highly Energy-Efficient SRAM With Hierarchical Bit Line Charge-Sharing Method Using Non-Selected Bit Line Charges. J. Solid-State Circuits 48(4): 924-931 (2013) |
| c72 | | Shunta Iguchi, Akira Saito, Kentaro Honda, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya: 315MHz OOK transceiver with 38-µW receiver and 36-µW transmitter in 40-nm CMOS. ASP-DAC 2013: 93-94 |
| c71 | | Xin Zhang, Po-Hung Chen, Yoshikatsu Ryu, Koichi Ishida, Yasuyuki Okuma, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya: A low voltage buck DC-DC converter using on-chip gate boost technique in 40nm CMOS. ASP-DAC 2013: 109-110 |
| c70 | | Hiroshi Fuketa, Kazuaki Yoshioka, Yasuhiro Shinozuka, Koichi Ishida, Tomoyuki Yokota, Naoji Matsuhisa, Yusuke Inoue, Masaki Sekino, Tsuyoshi Sekitani, Makoto Takamiya, Takao Someya, Takayasu Sakurai: 1µm-thickness 64-channel surface electromyogram measurement sheet with 2V organic transistors for prosthetic hand control. ISSCC 2013: 104-105 |
| c69 | | Hiroshi Fuketa, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai: Intermittent resonant clocking enabling power reduction at any clock frequency for 0.37V 980kHz near-threshold logic circuits. ISSCC 2013: 436-437 |
| 2012 | ||
| j45 | | Lechang Liu, Takayasu Sakurai, Makoto Takamiya: A 315 MHz Power-Gated Ultra Low Power Transceiver in 40 nm CMOS for Wireless Sensor Network. IEICE Transactions 95-C(6): 1035-1041 (2012) |
| j44 | | Naoki Masunaga, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya: EMI Camera LSI (EMcam) with On-Chip Loop Antenna Matrix to Measure EMI Noise Spectrum and Distribution. IEICE Transactions 95-C(6): 1059-1066 (2012) |
| j43 | | Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai: A 100-V AC Energy Meter Integrating 20-V Organic CMOS Digital and Analog Circuits With a Floating Gate for Process Variation Compensation and a 100-V Organic pMOS Rectifier. J. Solid-State Circuits 47(1): 301-309 (2012) |
| j42 | | Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: Startup Techniques for 95 mV Step-Up Converter by Capacitor Pass-On Scheme and VTH-Tuned Oscillator With Fixed Charge Programming. J. Solid-State Circuits 47(5): 1252-1260 (2012) |
| j41 | | Po-Hung Chen, Xin Zhang, Koichi Ishida, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: An 80 mV Startup Dual-Mode Boost Converter by Charge-Pumped Pulse Generator and Threshold Voltage Tuned Oscillator With Hot Carrier Injection. J. Solid-State Circuits 47(11): 2554-2562 (2012) |
| j40 | | Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya: A 1-V-Input Switched-Capacitor Voltage Converter With Voltage-Reference-Free Pulse-Density Modulation. IEEE Trans. on Circuits and Systems 59-II(6): 361-365 (2012) |
| j39 | | Ryo Takahashi, Hidehiro Takata, Tadashi Yasufuku, Hiroshi Fuketa, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: Large Within-Die Gate Delay Variations in Sub-Threshold Logic Circuits at Low Temperature. IEEE Trans. on Circuits and Systems 59-II(12): 918-921 (2012) |
| j38 | | Xin Zhang, Koichi Ishida, Hiroshi Fuketa, Makoto Takamiya, Takayasu Sakurai: On-Chip Measurement System for Within-Die Delay Variation of Individual Standard Cells in 65-nm CMOS. IEEE Trans. VLSI Syst. 20(10): 1876-1880 (2012) |
| c68 | | Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: A 120-mV input, fully integrated dual-mode charge pump in 65-nm CMOS for thermoelectric energy harvester. ASP-DAC 2012: 469-470 |
| c67 | | Hiroshi Fuketa, Ryo Takahashi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: Increase of crosstalk noise due to imbalanced threshold voltage between NMOS and PMOS in sub-threshold logic circuits. CICC 2012: 1-4 |
| c66 | | Shunta Iguchi, Akira Saito, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya: 2.1 Times increase of drain efficiency by dual supply voltage scheme in 315MHz class-F Power amplifier at output power of -20dBm. ESSCIRC 2012: 345-348 |
| c65 | | Akira Saito, Yun Fei Zheng, Kazunori Watanabe, Takayasu Sakurai, Makoto Takamiya: 0.35V, 4.1μW, 39MHz crystal oscillator in 40nm CMOS. ISLPED 2012: 333-338 |
| c64 | | Tadashi Yasufuku, Koji Hirairi, Yu Pu, Yun Fei Zheng, Ryo Takahashi, Masato Sasaki, Hiroshi Fuketa, Atsushi Muramatsu, Masahiro Nomura, Hirofumi Shinohara, Makoto Takamiya, Takayasu Sakurai: 24% Power reduction by post-fabrication dual supply voltage control of 64 voltage domains in VDDmin limited ultra low voltage logic circuits. ISQED 2012: 586-591 |
| c63 | | Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Yasuhiro Shinozuka, Hiroshi Fuketa, Tomoyuki Yokota, Ute Zschieschang, Hagen Klauk, Gregory Tortissier, Tsuyoshi Sekitani, Makoto Takamiya, Hiroshi Toshiyoshi, Takao Someya, Takayasu Sakurai: Insole pedometer with piezoelectric energy harvester and 2V organic digital and analog circuits. ISSCC 2012: 308-310 |
| c62 | | Koji Hirairi, Yasuyuki Okuma, Hiroshi Fuketa, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: 13% Power reduction in 16b integer unit in 40nm CMOS by adaptive power supply voltage control with parity-based error prediction and detection (PEPD) and fully integrated digital LDO. ISSCC 2012: 486-488 |
| 2011 | ||
| j37 | | Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: 0.18-V Input Charge Pump with Forward Body Bias to Startup Boost Converter for Energy Harvesting Applications. IEICE Transactions 94-C(4): 598-604 (2011) |
| j36 | | Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai: 0.5-V Input Digital Low-Dropout Regulator (LDO) with 98.7% Current Efficiency in 65 nm CMOS. IEICE Transactions 94-C(6): 938-944 (2011) |
| j35 | | Xin Zhang, Yu Pu, Koichi Ishida, Yoshikatsu Ryu, Yasuyuki Okuma, Po-Hung Chen, Takayasu Sakurai, Makoto Takamiya: A Variable Output Voltage Switched-Capacitor DC-DC Converter with Pulse Density and Width Modulation (PDWM) for 57% Ripple Reduction at Low Output Voltage. IEICE Transactions 94-C(6): 953-959 (2011) |
| j34 | | Lechang Liu, Takayasu Sakurai, Makoto Takamiya: 0.6 V Voltage Shifter and Clocked Comparator for Sampling Correlation-Based Impulse Radio UWB Receiver. IEICE Transactions 94-C(6): 985-991 (2011) |
| j33 | | Katsuyuki Ikeuchi, Hideki Kusamitsu, Mutsuo Daito, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai: 1 Gb/s, 50 µm × 50 µm Pads on Board Wireless Connector Based on Track-and-Charge Scheme Allowing Contacted Signaling. IEICE Transactions 94-C(6): 992-998 (2011) |
| j32 | | Tadashi Yasufuku, Yasumi Nakamura, Piao Zhe, Makoto Takamiya, Takayasu Sakurai: Power Supply Voltage Dependence of Within-Die Delay Variation of Regular Manual Layout and Irregular Place-and-Route Layout. IEICE Transactions 94-C(6): 1072-1075 (2011) |
| j31 | | Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai: User Customizable Logic Paper (UCLP) With Sea-Of Transmission-Gates (SOTG) of 2-V Organic CMOS and Ink-Jet Printed Interconnects. J. Solid-State Circuits 46(1): 285-292 (2011) |
| j30 | | Lechang Liu, Takayasu Sakurai, Makoto Takamiya: A Charge-Domain Auto- and Cross-Correlation Based Data Synchronization Scheme With Power- and Area-Efficient PLL for Impulse Radio UWB Receiver. J. Solid-State Circuits 46(6): 1349-1359 (2011) |
| j29 | | Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi: 1.8 V Low-Transient-Energy Adaptive Program-Voltage Generator Based on Boost Converter for 3D-Integrated NAND Flash SSD. J. Solid-State Circuits 46(6): 1478-1487 (2011) |
| j28 | | Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai: Capacitively Coupled Non-Contact Probing Circuits for Membrane-Based Wafer-Level Simultaneous Testing. J. Solid-State Circuits 46(10): 2386-2395 (2011) |
| j27 | | Yu Pu, Xin Zhang, Katsuyuki Ikeuchi, Atsushi Muramatsu, Atsushi Kawasumi, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: Post-Silicon Clock Deskew Employing Hot-Carrier Injection Trimming With On-Chip Skew Monitoring and Auto-Stressing Scheme for Sub/Near Threshold Digital Circuits. IEEE Trans. on Circuits and Systems 58-II(5): 294-298 (2011) |
| c61 | | Katsuyuki Ikeuchi, Makoto Takamiya, Takayasu Sakurai: Through Silicon Capacitive Coupling (TSCC) interface for 3D stacked dies. 3DIC 2011: 1-5 |
| c60 | | Xin Zhang, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai: An on-chip characterizing system for within-die delay variation measurement of individual standard cells in 65-nm CMOS. ASP-DAC 2011: 109-110 |
| c59 | | Shinichi Moriwaki, Atsushi Kawasumi, Toshikazu Suzuki, Takayasu Sakurai, Shinji Miyano: 0.4V SRAM with bit line swing suppression charge share hierarchical bit line scheme. CICC 2011: 1-4 |
| c58 | | Hiroshi Fuketa, Satoshi Iida, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates. DAC 2011: 984-989 |
| c57 | | Atsushi Muramatsu, Tadashi Yasufuku, Masahiro Nomura, Makoto Takamiya, Hirofumi Shinohara, Takayasu Sakurai: 12% Power reduction by within-functional-block fine-grained adaptive dual supply voltage control in logic circuits with 42 voltage domains. ESSCIRC 2011: 191-194 |
| c56 | | Tadashi Yasufuku, Satoshi Iida, Hiroshi Fuketa, Koji Hirairi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai: Investigation of determinant factors of minimum operating voltage of logic gates in 65-nm CMOS. ISLPED 2011: 21-26 |
| c55 | | |
| c54 | | Hiroshi Fuketa, Koji Hirairi, Tadashi Yasufuku, Makoto Takamiya, Masahiro Nomura, Hirofumi Shinohara, Takayasu Sakurai: 12.7-times energy efficiency increase of 16-bit integer unit by power supply voltage (VDD) scaling from 1.2v to 310mv enabled by contention-less flip-flops (CLFF) and separated VDD between flip-flops and combinational logics. ISLPED 2011: 163-168 |
| c53 | | Kentaro Honda, Katsuyuki Ikeuchi, Masahiro Nomura, Makoto Takamiya, Takayasu Sakurai: Reduction of minimum operating voltage (VDDmin) of CMOS logic circuits with post-fabrication automatically selective charge injection. ISLPED 2011: 175-180 |
| c52 | | Jan M. Rabaey, Hugo De Man, Mark Horowitz, Takayasu Sakurai, Jack Sun, Dan Dobberpuhl, Kiyoo Itoh, Philippe Magarshack, Asad A. Abidi, Hermann Eul: Beyond the horizon: The next 10x reduction in power - Challenges and solutions. ISSCC 2011: 31 |
| c51 | | Po-Hung Chen, Koichi Ishida, Katsuyuki Ikeuchi, Xin Zhang, Kentaro Honda, Yasuyuki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: A 95mV-startup step-up converter with Vth-tuned oscillator by fixed-charge programming and capacitor pass-on scheme. ISSCC 2011: 216-218 |
| c50 | | Koichi Ishida, Tsung-Ching Huang, Kentaro Honda, Tsuyoshi Sekitani, Hiroyoshi Nakajima, Hiroki Maeda, Makoto Takamiya, Takao Someya, Takayasu Sakurai: 100V AC power meter system-on-a-film (SoF) integrating 20V organic CMOS digital and analog circuits with floating gate for process-variation compensation and 100V organic PMOS rectifier. ISSCC 2011: 218-220 |
| 2010 | ||
| j26 | | Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi: Inductor and TSV Design of 20-V Boost Converter for Low Power 3D Solid State Drive with NAND Flash Memories. IEICE Transactions 93-C(3): 317-323 (2010) |
| j25 | | Tadashi Yasufuku, Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai: Difficulty of Power Supply Voltage Scaling in Large Scale Subthreshold Logic Circuits. IEICE Transactions 93-C(3): 332-339 (2010) |
| j24 | | Lechang Liu, Zhiwei Zhou, Takayasu Sakurai, Makoto Takamiya: A 1.76 mW, 100 Mbps Impulse Radio UWB Receiver with Multiple Sampling Correlators Eliminating Need for Phase Synchronization in 65-nm CMOS. IEICE Transactions 93-C(6): 796-802 (2010) |
| j23 | | Mitsuko Saito, Yasufumi Sugimori, Yoshinori Kohama, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda: 2 Gb/s 15 pJ/b/chip Inductive-Coupling Programmable Bus for NAND Flash Memory Stacking. J. Solid-State Circuits 45(1): 134-141 (2010) |
| j22 | | Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai: Stretchable EMI Measurement Sheet With 8 ˟ 8 Coil Array, 2 V Organic CMOS Decoder, and 0.18 μ m Silicon CMOS LSIs for Electric and Magnetic Field Detection. J. Solid-State Circuits 45(1): 249-259 (2010) |
| j21 | | Youngsoo Shin, Jun Seomun, Kyu-Myung Choi, Takayasu Sakurai: Power gating: Circuits, design methodologies, and best practice for standard-cell VLSI designs. ACM Trans. Design Autom. Electr. Syst. 15(4) (2010) |
| c49 | | Koichi Ishida, Koichi Takemura, Kazuhiro Baba, Makoto Takamiya, Takayasu Sakurai: 3D stacked buck converter with 15μm thick spiral inductor on silicon interposer for fine-grain power-supply voltage control in SiP's. 3DIC 2010: 1-4 |
| c48 | | Gil-Su Kim, Katsuyuki Ikeuchi, Mutsuo Daito, Makoto Takamiya, Takayasu Sakurai: A high-speed, low-power capacitive-coupling transceiver for wireless wafer-level testing systems. 3DIC 2010: 1-4 |
| c47 | | Po-Hung Chen, Koichi Ishida, Xin Zhang, Yasuaki Okuma, Yoshikatsu Ryu, Makoto Takamiya, Takayasu Sakurai: 0.18-V input charge pump with forward body biasing in startup circuit using 65nm CMOS. CICC 2010: 1-4 |
| c46 | | Naoki Masunaga, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai: EMI Camera LSI (EMcam) with 12 × 4 on-chip loop antenna matrix in 65-nm CMOS to measure EMI noise distribution with 60-µm spatial precision. CICC 2010: 1-4 |
| c45 | | Yasuyuki Okuma, Koichi Ishida, Yoshikatsu Ryu, Xin Zhang, Po-Hung Chen, Kazunori Watanabe, Makoto Takamiya, Takayasu Sakurai: 0.5-V input digital LDO with 98.7% current efficiency and 2.7-µA quiescent current in 65nm CMOS. CICC 2010: 1-4 |
| c44 | | Makoto Takamiya, Koichi Ishida, Tsuyoshi Sekitani, Takao Someya, Takayasu Sakurai: Design of large area electronics with organic transistors. ICCAD 2010: 500-503 |
| c43 | | Yu Pu, Xin Zhang, Jim Huang, Atsushi Muramatsu, Masahiro Nomura, Koji Hirairi, Hidehiro Takata, Taro Sakurabayashi, Shinji Miyano, Makoto Takamiya, Takayasu Sakurai: Misleading energy and performance claims in sub/near threshold digital systems. ICCAD 2010: 625-631 |
| c42 | | Koichi Ishida, Naoki Masunaga, Ryo Takahashi, Tsuyoshi Sekitani, Shigeki Shino, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai: User Customizable Logic Paper (UCLP) with organic sea-of-transmission-gates (SOTG) architecture and ink-jet printed interconnects. ISSCC 2010: 138-139 |
| c41 | | Mutsuo Daito, Yoshiro Nakata, Satoshi Sasaki, Hiroyuki Gomyo, Hideki Kusamitsu, Yoshio Komoto, Kunihiko Iizuka, Katsuyuki Ikeuchi, Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai: Capacitively coupled non-contact probing circuits for membrane-based wafer-level simultaneous testing. ISSCC 2010: 144-145 |
| c40 | | Pascal Urard, Ken Takeuchi, Kerry Bernstein, Hideto Hidaka, Michael Phan, Joo Sun Choi, Bob Payne, Vladimir Stojanovic, Kees van Berkel, Takayasu Sakurai: Silicon 3D-integration technology and systems. ISSCC 2010: 510-511 |
| c39 | | Azeez Bhavnagarwala, Shekhar Borkar, Takayasu Sakurai, Siva Narendra: The semiconductor industry in 2025. ISSCC 2010: 534-535 |
| 2009 | ||
| j20 | | Yasumi Nakamura, Makoto Takamiya, Takayasu Sakurai: An On-Chip Noise Canceller with High Voltage Supply Lines for Nanosecond-Range Power Supply Noise. IEICE Transactions 92-C(4): 468-474 (2009) |
| j19 | | Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai: A 100 Mbps, 4.1 pJ/bit Threshold Detection-Based Impulse Radio UWB Transceiver in 90 nm CMOS. IEICE Transactions 92-C(6): 769-776 (2009) |
| j18 | | Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai: A 25-mV-Sensitivity 2-Gb/s Optimum-Logic-Threshold Capacitive-Coupling Receiver for Wireless Wafer Probing Systems. IEEE Trans. on Circuits and Systems 56-II(9): 709-713 (2009) |
| j17 | | Lechang Liu, Makoto Takamiya, Tsuyoshi Sekitani, Yoshiaki Noguchi, Shintaro Nakano, Koichiro Zaitsu, Tadahiro Kuroda, Takao Someya, Takayasu Sakurai: A 107-pJ/bit 100-kb/s 0.18- muhboxm Capacitive-Coupling Transceiver With Data Edge Signaling and DC Power-Free Pulse Detector for Printable Communication Sheet. IEEE Trans. on Circuits and Systems 56-I(11): 2511-2518 (2009) |
| c38 | | Gil-Su Kim, Makoto Takamiya, Takayasu Sakurai: A capacitive coupling interface with high sensitivity for wireless wafer testing. 3DIC 2009: 1-5 |
| c37 | | Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi: Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. 3DIC 2009: 1-4 |
| c36 | | Lechang Liu, Yoshio Miyamoto, Zhiwei Zhou, Kosuke Sakaida, Jisun Ryu, Koichi Ishida, Makoto Takamiya, Takayasu Sakurai: A 100Mbps, 0.19mW asynchronous threshold detector with DC power-free pulse discrimination for impulse UWB receiver. ASP-DAC 2009: 97-98 |
| c35 | | Katsuyuki Ikeuchi, Kosuke Sakaida, Koichi Ishida, Takayasu Sakurai, Makoto Takamiya: Switched Resonant Clocking (SRC) scheme enabling dynamic frequency scaling and low-speed test. CICC 2009: 33-36 |
| c34 | | Tadashi Yasufuku, Koichi Ishida, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi: Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. ISLPED 2009: 87-92 |
| c33 | | Koichi Ishida, Tadashi Yasufuku, Shinji Miyamoto, Hiroto Nakai, Makoto Takamiya, Takayasu Sakurai, Ken Takeuchi: A 1.8V 30nJ adaptive program-voltage (20V) generator for 3D-integrated NAND flash SSD. ISSCC 2009: 238-239 |
| c32 | | Yasufumi Sugimori, Yoshinori Kohama, Mitsuko Saito, Yoichi Yoshida, Noriyuki Miura, Hiroki Ishikuro, Takayasu Sakurai, Tadahiro Kuroda: A 2Gb/s 15pJ/b/chip Inductive-Coupling programmable bus for NAND Flash memory stacking. ISSCC 2009: 244-245 |
| c31 | | Koichi Ishida, Naoki Masunaga, Zhiwei Zhou, Tadashi Yasufuku, Tsuyoshi Sekitani, Ute Zschieschang, Hagen Klauk, Makoto Takamiya, Takao Someya, Takayasu Sakurai: A stretchable EMI measurement sheet with 8×8 coil array, 2V organic CMOS decoder, and -70dBm EMI detection circuits in 0.18¼m CMOS. ISSCC 2009: 472-473 |
| 2008 | ||
| c30 | | Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai: Increasing minimum operating voltage (VDDmin) with number of CMOS logic gates and experimental verification with up to 1Mega-stage ring oscillators. ISLPED 2008: 117-122 |
| c29 | | |
| c28 | | Taro Niiyama, Piao Zhe, Koichi Ishida, Masami Murakata, Makoto Takamiya, Takayasu Sakurai: Dependence of Minimum Operating Voltage (VDDmin) on Block Size of 90-nm CMOS Ring Oscillators and its Implications in Low Power DFM. ISQED 2008: 133-136 |
| 2007 | ||
| j16 | | Fayez Robert Saliba, Hiroshi Kawaguchi, Takayasu Sakurai: A Self-Alignment Row-by-Row Variable-VDD Scheme Reducing 90% of Active-Leakage Power in SRAM's. IEICE Transactions 90-C(4): 743-748 (2007) |
| j15 | | Koichi Ishida, Atit Tamtrakarn, Hiroki Ishikuro, Makoto Takamiya, Takayasu Sakurai: An Outside-Rail Opamp Design Relaxing Low-Voltage Constraint on Future Scaled Transistors. IEICE Transactions 90-C(4): 786-792 (2007) |
| j14 | | Kiichi Niitsu, Noriyuki Miura, Mari Inoue, Yoshihiro Nakagawa, Masamoto Tago, Masayuki Mizuno, Takayasu Sakurai, Tadahiro Kuroda: Daisy Chain Transmitter for Power Reduction in Inductive-Coupling CMOS Link. IEICE Transactions 90-C(4): 829-835 (2007) |
| j13 | | Hiroshi Kawaguchi, Danardono Dwi Antono, Takayasu Sakurai: Closed-Form Expressions for Crosstalk Noise and Worst-Case Delay on Capacitively Coupled Distributed RC Lines. IEICE Transactions 90-A(12): 2669-2681 (2007) |
| c27 | | Takayasu Sakurai: Meeting with the Forthcoming IC Design "The Era of Power, Variability and NRE Explosion and a Bit of the Future". ASP-DAC 2007 |
| c26 | | |
| 2006 | ||
| j12 | | Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai: Low-Power Low-Leakage FPGA Design Using Zigzag Power Gating, Dual-VTH/VDD and Micro-VDD-Hopping. IEICE Transactions 89-C(3): 280-286 (2006) |
| j11 | | Daisuke Mizoguchi, Noriyuki Miura, Takayasu Sakurai, Tadahiro Kuroda: A 1.2 Gbps Non-contact 3D-Stacked Inter-Chip Data Communications Technology. IEICE Transactions 89-C(3): 320-326 (2006) |
| j10 | | Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai: Trends of On-Chip Interconnects in Deep Sub-Micron VLSI. IEICE Transactions 89-C(3): 392-394 (2006) |
| j9 | | Danardono Dwi Antono, Kenichi Inagaki, Hiroshi Kawaguchi, Takayasu Sakurai: Simple Waveform Model of Inductive Interconnects by Delayed Quadratic Transfer Function with Application to Scaling Trend of Inductive Effects in VLSI's. IEICE Transactions 89-A(12): 3569-3578 (2006) |
| j8 | | Kyeong-Sik Min, Hun-Dae Choi, H.-Y. Choi, Hiroshi Kawaguchi, Takayasu Sakurai: Leakage-suppressed clock-gating circuit with Zigzag Super Cut-off CMOS (ZSCCMOS) for leakage-dominant sub-70-nm and sub-1-V-V/sub DD/ LSIs. IEEE Trans. VLSI Syst. 14(4): 430-435 (2006) |
| c25 | | Koichi Ishida, Atit Tamtrakarn, Takayasu Sakurai: A 0.5-V sigma-delta modulator using analog T-switch scheme for the subthreshold leakage suppression. ASP-DAC 2006: 98-99 |
| 2005 | ||
| j7 | | Kyeong-Sik Min, Kouichi Kanda, Hiroshi Kawaguchi, Kenichi Inagaki, Fayez Robert Saliba, Hoon-Dae Choi, Hyun-Young Choi, Daejeong Kim, Dong Myong Kim, Takayasu Sakurai: Row-by-Row Dynamic Source-Line Voltage Control (RRDSV) Scheme for Two Orders of Magnitude Leakage Current Reduction of Sub-1-V-VDD SRAM's. IEICE Transactions 88-C(4): 760-767 (2005) |
| j6 | | Keisuke Toyama, Satoshi Misaka, Kazuo Aisaka, Toshiyuki Aritsuka, Kunio Uchiyama, Koichiro Ishibashi, Hiroshi Kawaguchi, Takayasu Sakurai: Frequency-voltage cooperative CPU power control: A design rule and its application by feedback prediction. Systems and Computers in Japan 36(6): 39-48 (2005) |
| j5 | | Hiroshi Kawaguchi, Youngsoo Shin, Takayasu Sakurai: /spl mu/ITRON-LP: power-conscious real-time OS based on cooperative voltage scaling for multimedia applications. IEEE Transactions on Multimedia 7(1): 67-74 (2005) |
| c24 | | Canh Quang Tran, Hiroshi Kawaguchi, Takayasu Sakurai: More than two orders of magnitude leakage current reduction in look-up table for FPGAs. ISCAS (5) 2005: 4701-4704 |
| 2003 | ||
| c23 | | Jan M. Rabaey, Dennis Sylvester, David Blaauw, Kerry Bernstein, Jerry Frenkil, Mark Horowitz, Wolfgang Nebel, Takayasu Sakurai, Andrew Yang: Reshaping EDA for power. DAC 2003: 15 |
| 2002 | ||
| j4 | | Seongsoo Lee, Seungjun Lee, Takayasu Sakurai: Energy-Constrained VDD Hopping Scheme with Run-Time Power Estimation for Low-Power Real-Time VLSI Systems. Journal of Circuits, Systems, and Computers 11(6): 601-620 (2002) |
| c22 | | |
| c21 | | Kyeong-Sik Min, Young-Hee Kim, Jin-Hong Ahn, Jin-Yong Chung, Takayasu Sakurai: CMOS charge pumps using cross-coupled charge transfer switches with improved voltage pumping gain and low gate-oxide stress for low-voltage memory circuits. ISCAS (5) 2002: 545-548 |
| c20 | | Koichi Nose, Takayasu Sakurai: Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. ISLPED 2002: 24-29 |
| c19 | | Takayasu Sakurai: Low-Power and High-Speed V VLSI Design with Low Supply Voltage through Cooperation between Levels (invited). ISQED 2002: 445-450 |
| 2001 | ||
| c18 | | Youngsoo Shin, Takayasu Sakurai: Coupling-Driven Bus Design for Low-Power Application-Specific Systems. DAC 2001: 750-753 |
| c17 | | Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai: An LSI for VDD-hopping and MPEG4 system based on the chip. ISCAS (4) 2001: 918-921 |
| c16 | | Takashi Inukai, Toshiro Hiramoto, Takayasu Sakurai: Variable threshold CMOS (VTCMOS) in series connected circuits. ISLPED 2001: 201-206 |
| c15 | | Masayuki Hirabayashi, Koichi Nose, Takayasu Sakurai: Design methodology and optimization strategy for dual-VTH scheme using commercially available tools. ISLPED 2001: 283-286 |
| c14 | | Youngsoo Shin, Takayasu Sakurai: Estimation of power distribution in VLSI interconnects. ISLPED 2001: 370-375 |
| 2000 | ||
| j3 | | Koichi Nose, Takayasu Sakurai: Analysis and future trend of short-circuit power. IEEE Trans. on CAD of Integrated Circuits and Systems 19(9): 1023-1030 (2000) |
| c13 | | Seongsoo Lee, Takayasu Sakurai: Run-time power control scheme using software feedback loop for low-power real-time application. ASP-DAC 2000: 381-386 |
| c12 | | Koichi Nose, Takayasu Sakurai: Optimization of VDD and VTH for low-power and high speed applications. ASP-DAC 2000: 469-474 |
| c11 | | Nguyen Minh Duc, Takayasu Sakurai: Compact yet high performance (CyHP) library for short time-to-market with new technologies. ASP-DAC 2000: 475-480 |
| c10 | | |
| c9 | | Seongsoo Lee, Takayasu Sakurai: Run-time voltage hopping for low-power real-time systems. DAC 2000: 806-809 |
| c8 |  | Youngsoo Shin, Kiyoung Choi, Takayasu Sakurai: Power Optimization of Real-Time Embedded Systems on Variable Speed Processors. ICCAD 2000: 365-368 |
| c7 | | Koichi Nose, Soo-Ik Chae, Takayasu Sakurai: Voltage dependent gate capacitance and its impact in estimating power and delay of CMOS digital circuits with low supply voltage (poster session). ISLPED 2000: 228-230 |
| c6 | | Takayasu Sakurai: Reducing Power Consumption of CMOS VLSI's through VDD and VTH Control. ISQED 2000: 417-424 |
| 1998 | ||
| c5 | | Hiroshi Kawaguchi, Takayasu Sakurai: Delay and Noise Formulas for Capacitively Coupled Distributed RC Lines. ASP-DAC 1998: 35-43 |
| c4 | | Koichi Nose, Takayasu Sakurai: Integrated Current Sensing Device for Micro IDDQ Test. Asian Test Symposium 1998: 323-326 |
| c3 | | Seiji Takeuchi, Takayasu Sakurai: A fine-grain, current mode scheme for VLSI proximity search engine. ICCD 1998: 184-185 |
| 1996 | ||
| j2 | | Tadahiro Kuroda, Takayasu Sakurai: Threshold-Volgage control schemes through substrate-bias for low-power high-speed CMOS LSI design. VLSI Signal Processing 13(2-3): 191-201 (1996) |
| c2 | | Tadahiro Kuroda, Tetsuya Fujita, Shinji Mita, Toshiaki Mori, Kenji Matsuo, Masakazu Kakumu, Takayasu Sakurai: Substrate noise influence on circuit performance in variable threshold-voltage scheme. ISLPED 1996: 309-312 |
| 1993 | ||
| c1 | | Takayasu Sakurai: High-Speed Circuit Design with Scaled-Down MOSFET's and Low Supply Voltage. ISCAS 1993: 1487-1490 |
| 1992 | ||
| j1 | | Takayasu Sakurai, Bill Lin, A. Richard Newton: Fast simulated diffusion: an optimization algorithm for multiminimum problems and its application to MOSFET model parameter extraction. IEEE Trans. on CAD of Integrated Circuits and Systems 11(2): 228-234 (1992) |
Colors in the list of coauthors
Last update Thu May 23 14:16:34 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page