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O. Sarbishei
Omid Sarbishei
2010 – today
- 2013
[j4]Omid Sarbishei, Katarzyna Radecka: On the Fixed-Point Accuracy Analysis and Optimization of Polynomial Specifications. IEEE Trans. on CAD of Integrated Circuits and Systems 32(6): 831-844 (2013)- 2012
- [j3]Omid Sarbishei, Katarzyna Radecka, Zeljko Zilic: Analytical Optimization of Bit-Widths in Fixed-Point LTI Systems. IEEE Trans. on CAD of Integrated Circuits and Systems 31(3): 343-355 (2012)
- [c12]Omid Sarbishei, Katarzyna Radecka: Fixed-point accuracy analysis of datapaths with mixed CORDIC and polynomial computations. ASP-DAC 2012: 789-794
- [c11]Atena Roshan Fekr, Majid Janidarmian, Omid Sarbishei, Benjamin Nahill, Katarzyna Radecka, Zeljko Zilic: MSE minimization and fault-tolerant data fusion for multi-sensor systems. ICCD 2012: 445-452
- [c10]Omid Sarbishei, Katarzyna Radecka: Verification of fixed-point datapaths with comparator units using Constrained Arithmetic Transform (CAT). ISCAS 2012: 592-595
- 2011
- [c9]Omid Sarbishei, Katarzyna Radecka: On the Fixed-Point Accuracy Analysis and Optimization of FFT Units with CORDIC Multipliers. IEEE Symposium on Computer Arithmetic 2011: 62-69
- [c8]O. Sarbishei, Katarzyna Radecka: Analysis of Mean-Square-Error (MSE) for fixed-point FFT units. ISCAS 2011: 1732-1735
- 2010
- [j2]O. Sarbishei, Mohammad Maymandi-Nejad: A Novel Overlap-Based Logic Cell: An Efficient Implementation of Flip-Flops With Embedded Logic. IEEE Trans. VLSI Syst. 18(2): 222-231 (2010)
- [c7]O. Sarbishei, Yu Pang, Katarzyna Radecka: Analysis of range and precision for fixed-point linear arithmetic circuits with feedbacks. HLDVT 2010: 25-32
- [c6]O. Sarbishei, Katarzyna Radecka: Analysis of precision for scaling the intermediate variables in fixed-point arithmetic circuits. ICCAD 2010: 739-745
2000 – 2009
- 2009
- [j1]O. Sarbishei, M. Tabandeh, Bijan Alizadeh, Masahiro Fujita: A Formal Approach for Debugging Arithmetic Circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 28(5): 742-754 (2009)
- [c5]O. Sarbishei, Bijan Alizadeh, Masahiro Fujita: Polynomial datapath optimization using partitioning and compensation heuristics. DAC 2009: 931-936
- [c4]O. Sarbishei, M. Tabandeh, Bijan Alizadeh, Masahiro Fujita: High-level optimization of integer multipliers over a finite bit-width with verification capabilities. MEMOCODE 2009: 56-65
- 2008
- [c3]O. Sarbishei, Bijan Alizadeh, Masahiro Fujita: Arithmetic Circuits Verification without Looking for Internal Equivalences. MEMOCODE 2008: 7-16
- 2007
- [c2]O. Sarbishei, Mohammad Maymandi-Nejad: Power-Delay Efficient Overlap-Based Charge-Sharing Free Pseudo-Dynamic D Flip-Flops. ISCAS 2007: 637-640
- [c1]Omid Sarbishei, Vahid Mohtashami: A high-performance architecture for irregular LDPC decoding algorithm using input-multiplexing method. ISSPA 2007: 1-4
Coauthor Index
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last updated on 2013-05-22 20:48 CEST by the dblp team