Avesta Sasan

Avesta Sasan, Kiarash Amiri, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi: Variation Trained Drowsy Cache (VTD-Cache): A History Trained Variation Aware Drowsy Cache for Fine Grain Voltage Scaling. IEEE Trans. VLSI Syst. 20(4): 630-642 (2012)

Avesta Sasan, Houman Homayoun, Kiarash Amiri, Ahmed M. Eltawil, Fadi J. Kurdahi: History & Variation Trained Cache (HVT-Cache): A process variation aware and fine grain voltage scalable cache with active access history monitoring. ISQED 2012: 498-505

Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi: Inquisitive Defect Cache: A Means of Combating Manufacturing Induced Process Variation. IEEE Trans. VLSI Syst. 19(9): 1597-1609 (2011)

Houman Homayoun, Avesta Sasan, Jean-Luc Gaudiot, Alexander V. Veidenbaum: Reducing Power in All Major CAM and SRAM-Based Processor Units via Centralized, Dynamic Resource Size Management. IEEE Trans. VLSI Syst. 19(11): 2081-2094 (2011)

Houman Homayoun, Avesta Sasan, Alexander V. Veidenbaum, Hsin-Cheng Yao, Shahin Golshan, Payam Heydari: MZZ-HVS: Multiple Sleep Modes Zig-Zag Horizontal and Vertical Sleep Transistor Sharing to Reduce Leakage Power in On-Chip SRAM Peripheral Circuits. IEEE Trans. VLSI Syst. 19(12): 2303-2316 (2011)

Houman Homayoun, Avesta Sasan, Aseem Gupta, Alexander V. Veidenbaum, Fadi J. Kurdahi, Nikil Dutt: Multiple sleep modes leakage control in peripheral circuits of a all major SRAM-based processor units. Conf. Computing Frontiers 2010: 297-308

Houman Homayoun, Aseem Gupta, Alexander V. Veidenbaum, Avesta Sasan, Fadi J. Kurdahi, Nikil Dutt: RELOCATE: Register File Local Access Pattern Redistribution Mechanism for Power and Thermal Management in Out-of-Order Embedded Processor. HiPEAC 2010: 216-231

Mohammad A. Makhzan, Amin Khajeh, Ahmed M. Eltawil, Fadi J. Kurdahi: A Low Power JPEG2000 Encoder With Iterative and Fault Tolerant Error Concealment. IEEE Trans. VLSI Syst. 17(6): 827-837 (2009)

Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi: A fault tolerant cache architecture for sub 500mV operation: resizable data composer cache (RDC-cache). CASES 2009: 251-260

Avesta Sasan, Houman Homayoun, Ahmed M. Eltawil, Fadi J. Kurdahi: Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling. DATE 2009: 911-916

Mani Zarei, Amir Masoud Rahmani, Avesta Sasan, Mohammad Teshnehlab: Fuzzy Based Trust Estimation for Congestion Control in Wireless Sensor Networks. INCoS 2009: 233-236

Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum: Multiple sleep mode leakage control for cache peripheral circuits in embedded processors. CASES 2008: 197-206

Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum: Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency. DAC 2008: 68-71

Houman Homayoun, Mohammad A. Makhzan, Alexander V. Veidenbaum: ZZ-HVS: Zig-zag horizontal and vertical sleep transistor sharing to reduce leakage power in on-chip SRAM peripheral circuits. ICCD 2008: 699-706

Houman Homayoun, Sudeep Pasricha, Mohammad A. Makhzan, Alexander V. Veidenbaum: Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors. LCTES 2008: 71-78

Mohammad A. Makhzan, Ahmed M. Eltawil, Fadi J. Kurdahi: Architectural and algorithm level fault tolerant techniques for low power high yield multimedia devices. ICSAMOS 2008: 124-131

Houman Homayoun, Mohammad A. Makhzan, Jean-Luc Gaudiot, Alexander V. Veidenbaum: A centralized cache miss driven technique to improve processor power dissipation. ICSAMOS 2008: 195-202

Fadi J. Kurdahi, Ahmed M. Eltawil, Amin Khajeh Djahromi, Mohammad A. Makhzan, Stanley Cheng: Error-Aware Design. DSD 2007: 8-15

Mohammad A. Makhzan, Amin Khajeh Djahromi, Ahmed M. Eltawil, Fadi J. Kurdahi: Limits on voltage scaling for caches utilizing fault tolerant techniques. ICCD 2007: 488-495

Mohammad A. Makhzan, Kwei-Jay Lin: Solutions to a Complete Web Service Discovery and Composition. CEC/EEE 2006: 73