Visvesh S. Sathe

Visvesh S. Sathe, Srikanth Arekapudi, Alexander T. Ishii, Charles Ouyang, Marios C. Papaefthymiou, Samuel Naffziger: Resonant-Clock Design for a Power-Efficient, High-Volume x86-64 Microprocessor. J. Solid-State Circuits 48(1): 140-149 (2013)

Jerry C. Kao, Wei-Hsiang Ma, Visvesh S. Sathe, Marios C. Papaefthymiou: Energy-Efficient Low-Latency 600 MHz FIR With High-Overdrive Charge-Recovery Logic. IEEE Trans. VLSI Syst. 20(6): 977-988 (2012)

Visvesh S. Sathe, Srikanth Arekapudi, Charles Ouyang, Marios C. Papaefthymiou, Alexander T. Ishii, Samuel Naffziger: Resonant clock design for a power-efficient high-volume x86-64 microprocessor. ISSCC 2012: 68-70

Wei-Hsiang Ma, Jerry C. Kao, Visvesh S. Sathe, Marios C. Papaefthymiou: 187 MHz Subthreshold-Supply Charge-Recovery FIR. J. Solid-State Circuits 45(4): 793-803 (2010)

Hanh-Phuc Le, Michael D. Seeman, Seth Sanders, Visvesh S. Sathe, Samuel Naffziger, Elad Alon: A 32nm fully integrated reconfigurable switched-capacitor DC-DC converter delivering 0.55W/mm² at 81% efficiency. ISSCC 2010: 210-211

Visvesh S. Sathe, Juang-Ying Chueh, Joohee Kim, Conrad H. Ziesler, Suhwan Kim, Marios C. Papaefthymiou: Fast, efficient, recovering, and irreversible. Conf. Computing Frontiers 2005: 407-413

Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler: A GHz-class charge recovery logic. ISLPED 2005: 91-94

Visvesh S. Sathe, Marios C. Papaefthymiou, Conrad H. Ziesler: Boost Logic: A High Speed Energy Recovery Circuit Family. ISVLSI 2005: 22-27

Visvesh S. Sathe, Conrad H. Ziesler, Marios Papaefihymiou, Suhwan Kim, Stephen V. Kosonocky: A synchronous interface for SoCs with multiple clock domains. SoCC 2004: 173-174

Conrad H. Ziesler, Joohee Kim, Visvesh S. Sathe, Marios C. Papaefthymiou: A 225 MHz resonant clocked ASIC chip. ISLPED 2003: 48-53