Takashi Sato

Michihiro Shintani, Takashi Sato: Device-Parameter Estimation through IDDQ Signatures. IEICE Transactions 96-D(2): 303-313 (2013)

Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato: A Cost-Effective Selective TMR for Coarse-Grained Reconfigurable Architectures Based on DFG-Level Vulnerability Analysis. IEICE Transactions 96-C(4): 454-462 (2013)

Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato: Parallel Acceleration Scheme for Monte Carlo Based SSTA Using Generalized STA Processing Element. IEICE Transactions 96-C(4): 473-481 (2013)

Tetsuro Miyakawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato: Realization of frequency-domain circuit analysis through random walk. ASP-DAC 2013: 169-174

Michihiro Shintani, Takashi Sato: An adaptive current-threshold determination for IDDQ testing based on Bayesian process parameter estimation. ASP-DAC 2013: 614-619

Zoltán Endre Rákossy, Masayuki Hiromoto, Hiroshi Tsutsui, Takashi Sato, Yukihiro Nakamura, Hiroyuki Ochi: Hot-swapping architecture with back-biased testing for mitigation of permanent faults in functional unit array. DATE 2013: 535-540

Takashi Imagawa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato: A cost-effective selective TMR for heterogeneous coarse-grained reconfigurable architectures based on DFG-level vulnerability analysis. DATE 2013: 701-706

Junya Kawashima, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato: A Variability-Aware Energy-Minimization Strategy for Subthreshold Circuits. IEICE Transactions 95-A(12): 2242-2250 (2012)

Takashi Enami, Takashi Sato, Masanori Hashimoto: Power Distribution Network Optimization for Timing Improvement with Statistical Noise Model and Timing Analysis. IEICE Transactions 95-A(12): 2261-2271 (2012)

Hiromitsu Awano, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato: Bayesian Estimation of Multi-Trap RTN Parameters Using Markov Chain Monte Carlo Method. IEICE Transactions 95-A(12): 2272-2283 (2012)

Jyothi Velamala, Ketul Sutaria, Hirofumi Shimizu, Hiromitsu Awano, Takashi Sato, Yu Cao: Statistical aging under dynamic voltage scaling: A logarithmic model approach. CICC 2012: 1-4

Jyothi Bhaskarr Velamala, Ketul Sutaria, Takashi Sato, Yu Cao: Physics matters: statistical aging prediction under trapping/detrapping. DAC 2012: 139-144

Takashi Sato, Hiromitsu Awano, Hirofttmi Shimizu, Hiroshi Tsutsui, Hiroyuki Ochi: Statistical observations of NBTI-induced threshold voltage shifts on small channel-area devices. ISQED 2012: 306-311

Keita Emura, Takashi Sato: Flexible Group Key Exchange with On-demand Computation of Subgroup Keys Supporting Subgroup Key Randomization. SECRYPT 2012: 353-357

Michihiro Shintani, Takashi Sato: A Bayesian-based process parameter estimation using IDDQ current signature. VTS 2012: 86-91

Manabu Taura, Mary Ann Suico, Ryosuke Fukuda, Tomoaki Koga, Tsuyoshi Shuto, Takashi Sato, Saori Morino-Koga, Seiji Okada, Hirofumi Kai: MEF/ELF4 transactivation by E2F1 is inhibited by p53. Nucleic Acids Research 39(1): 76-88 (2011)

Tetsuya Hatano, Atsuko Miyaji, Takashi Sato: T-Robust Scalable Group Key Exchange Protocol with O(logn) Complexity. ACISP 2011: 189-207

Tetsuro Miyakawa, Koh Yamanaga, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato: Acceleration of random-walk-based linear circuit analysis using importance sampling. ACM Great Lakes Symposium on VLSI 2011: 211-216

Hiroshi Yuasa, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato: A fully pipelined implementation of Monte Carlo based SSTA on FPGAs. ISQED 2011: 785-790

Junya Kawashima, Hiroyuki Ochi, Hiroshi Tsutsui, Takashi Sato: A design strategy for sub-threshold circuits considering energy-minimization and yield-maximization. SoCC 2011: 57-62

Takumi Uezono, Kazuya Masu, Takashi Sato: A Time-Slicing Ring Oscillator for Capturing Time-Dependent Delay Degradation and Power Supply Voltage Fluctuation. IEICE Transactions 93-C(3): 324-331 (2010)

Koh Yamanaga, Shuhei Amakawa, Kazuya Masu, Takashi Sato: A Universal Equivalent Circuit Model for Ceramic Capacitors. IEICE Transactions 93-C(3): 347-354 (2010)

Toshiki Kanamoto, Takaaki Okumura, Katsuhiro Furukawa, Hiroshi Takafuji, Atsushi Kurokawa, Koutaro Hachiya, Tsuyoshi Sakata, Masakazu Tanaka, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto: Impact of Self-Heating in Wire Interconnection on Timing. IEICE Transactions 93-C(3): 388-392 (2010)

Takashi Sato, Toshiki Kanamoto, Saiko Kobayashi, Nobuhiko Goto, Takao Sato, Hitoshi Sugihara, Hiroo Masuda: A New LDMOS Transistor Macro-Modeling for Accurately Predicting Bias Dependence of Gate-Overlap Capacitance. IEICE Transactions 93-A(9): 1605-1611 (2010)

Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato: Linear Time Calculation of On-Chip Power Distribution Network Capacitance Considering State-Dependence. IEICE Transactions 93-A(12): 2409-2416 (2010)

Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato: Reliability Evaluation Environment for Exploring Design Space of Coarse-Grained Reconfigurable Architectures. IEICE Transactions 93-A(12): 2524-2532 (2010)

Zhangcai Huang, Atsushi Kurokawa, Masanori Hashimoto, Takashi Sato, Minglu Jiang, Yasuaki Inoue: Modeling the Overshooting Effect for CMOS Inverter Delay Analysis in Nanometer Technologies. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 250-260 (2010)

Kentaro Katayama, Shiho Hagiwara, Hiroshi Tsutsui, Hiroyuki Ochi, Takashi Sato: Sequential importance sampling for low-probability and high-dimensional SRAM yield analysis. ICCAD 2010: 703-708

Takashi Sato, Takumi Uezono, Noriaki Nakayama, Kazuya Masu: Decomposition of drain-current variation into gain-factor and threshold voltage variations. ISCAS 2010: 1053-1056

Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato: Scan based process parameter estimation through path-delay inequalities. ISCAS 2010: 3553-3556

Takanori Date, Shiho Hagiwara, Kazuya Masu, Takashi Sato: Robust importance sampling for efficient SRAM yield analysis. ISQED 2010: 15-21

Shiho Hagiwara, Koh Yamanaga, Ryo Takahashi, Kazuya Masu, Takashi Sato: Linear time calculation of state-dependent power distribution network capacitance. ISQED 2010: 75-80

Koh Yamanaga, Kazuya Masu, Takashi Sato: Application of generalized scattering matrix for prediction of power supply noise. SLIP 2010: 83-90

Takashi Imagawa, Masayuki Hiromoto, Hiroyuki Ochi, Takashi Sato: A routing architecture exploration for coarse-grained reconfigurable architecture with automated seu-tolerance evaluation. SoCC 2010: 248-253

Takumi Uezono, Tomoyuki Takahashi, Michihiro Shintani, Kazumi Hatayama, Kazuya Masu, Hiroyuki Ochi, Takashi Sato: Path clustering for adaptive test. VTS 2010: 15-20

Koh Yamanaga, Takashi Sato, Kazuya Masu: 2-Port Modeling Technique for Surface-Mount Passive Components Using Partial Inductance Concept. IEICE Transactions 92-A(4): 976-982 (2009)

Takaaki Okumura, Atsushi Kurokawa, Hiroo Masuda, Toshiki Kanamoto, Masanori Hashimoto, Hiroshi Takafuji, Hidenari Nakashima, Nobuto Ono, Tsuyoshi Sakata, Takashi Sato: Improvement in Computational Accuracy of Output Transition Time Variation Considering Threshold Voltage Variations. IEICE Transactions 92-A(4): 990-997 (2009)

Takumi Uezono, Takashi Sato, Kazuya Masu: One-Shot Voltage-Measurement Circuit Utilizing Process Variation. IEICE Transactions 92-A(4): 1024-1030 (2009)

Shiho Hagiwara, Takashi Sato, Kazuya Masu: Analytical Estimation of Path-Delay Variation for Multi-Threshold CMOS Circuits. IEICE Transactions 92-A(4): 1031-1038 (2009)

Tsuyoshi Sakata, Takaaki Okumura, Atsushi Kurokawa, Hidenari Nakashima, Hiroo Masuda, Takashi Sato, Masanori Hashimoto, Koutaro Hachiya, Katsuhiro Furukawa, Masakazu Tanaka, Hiroshi Takafuji, Toshiki Kanamoto: An Approach for Reducing Leakage Current Variation due to Manufacturing Variability. IEICE Transactions 92-A(12): 3016-3023 (2009)

Michihiro Shintani, Takumi Uezono, Tomoyuki Takahashi, Hiroyuki Ueyama, Takashi Sato, Kazumi Hatayama, Takashi Aikyo, Kazuya Masu: An Adaptive Test for Parametric Faults Based on Statistical Timing Information. Asian Test Symposium 2009: 151-156

Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera: Timing Analysis Considering Temporal Supply Voltage Fluctuation. IEICE Transactions 91-D(3): 655-660 (2008)

Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu: Application of Correlation-Based Regression Analysis for Improvement of Power Distribution Network. IEICE Transactions 91-A(4): 951-956 (2008)

Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu: An Evaluation Method of the Number of Monte Carlo STA Trials for Statistical Path Delay Analysis. IEICE Transactions 91-A(4): 957-964 (2008)

Kenta Yamada, Takashi Sato, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu, Shigetaka Kumashiro: Layout-Aware Compact Model of MOSFET Characteristics Variations Induced by STI Stress. IEICE Transactions 91-C(7): 1142-1150 (2008)

Takashi Sato, Hiroyuki Ueyama, Noriaki Nakayama, Kazuya Masu: Determination of optimal polynomial regression function to decompose on-die systematic and random variations. ASP-DAC 2008: 518-523

Masanori Imai, Takashi Sato, Noriaki Nakayama, Kazuya Masu: Non-parametric statistical static timing analysis: an SSTA framework for arbitrary distribution. DAC 2008: 698-701

Takashi Enami, Masanori Hashimoto, Takashi Sato: Decoupling capacitance allocation for timing with statistical noise model and timing analysis. ICCAD 2008: 420-425

Hiroyuki Kobayashi, Nobuto Ono, Takashi Sato, Jiro Iwai, Hidenari Nakashima, Takaaki Okumura, Masanori Hashimoto: Proposal of Metrics for SSTA Accuracy Evaluation. IEICE Transactions 90-A(4): 808-814 (2007)

Junki Seita, Hiroyuki Ito, Kenichi Okada, Takashi Sato, Kazuya Masu: A Multi-Drop Transmission-Line Interconnect in Si LSI. ASP-DAC 2007: 118-119

Shiho Hagiwara, Takumi Uezono, Takashi Sato, Kazuya Masu: Improvement of power distribution network using correlation-based regression analysis. ACM Great Lakes Symposium on VLSI 2007: 513-516

Takashi Sato, Takumi Uezono, Shiho Hagiwara, Kenichi Okada, Shuhei Amakawa, Noriaki Nakayama, Kazuya Masu: A MOS Transistor-Array for Accurate Measurement of Subthreshold Leakage Variation. ISQED 2007: 21-26

Takashi Sato, Shiho Hagiwara, Takumi Uezono, Kazuya Masu: Weakness Identification for Effective Repair of Power Distribution Network. PATMOS 2007: 222-231

Shuhei Amakawa, Takumi Uezono, Takashi Sato, Kenichi Okada, Kazuya Masu: Adaptable wire-length distribution with tunable occupation probability. SLIP 2007: 1-8

Koutaro Hachiya, Hiroyuki Kobayashi, Takaaki Okumura, Takashi Sato, Hiroki Oka: A Method to Derive SSO Design Rule Considering Jitter Constraint. IEICE Transactions 89-A(4): 865-872 (2006)

Takashi Sato, Junji Ichimiya, Nobuto Ono, Masanori Hashimoto: On-Chip Thermal Gradient Analysis Considering Interdependence between Leakage Power and Temperature. IEICE Transactions 89-A(12): 3491-3499 (2006)

Jun Usui, Hirotaka Hatayama, Takashi Sato, Yumi Furuoka, Naohito Okude: Paravie: dance entertainment system for everyone to express oneself with movement. Advances in Computer Entertainment Technology 2006: 30

Norihiro Kikuchi, Akihiko Kameyama, Shuuichi Nakaya, Hiromi Ito, Takashi Sato, Toshihide Shikanai, Yoriko Takahashi, Hisashi Narimatsu: The carbohydrate sequence markup language (CabosML): an XML description of carbohydrate structures. Bioinformatics 21(8): 1717-1718 (2005)

Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto: On-Chip Thermal Gradient Analysis and Temperature Flattening for SoC Design. IEICE Transactions 88-A(12): 3382-3389 (2005)

Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera: Successive Pad Assignment for Minimizing Supply Voltage Drop. IEICE Transactions 88-A(12): 3429-3436 (2005)

Takashi Sato, Masanori Hashimoto, Hidetoshi Onodera: Successive pad assignment algorithm to optimize number and location of power supply pad using incremental matrix inversion. ASP-DAC 2005: 723-728

Takashi Sato, Junji Ichimiya, Nobuto Ono, Koutaro Hachiya, Masanori Hashimoto: On-chip thermal gradient analysis and temperature flattening for SoC design. ASP-DAC 2005: 1074-1077

Masanori Hashimoto, Junji Yamaguchi, Takashi Sato, Hidetoshi Onodera: Timing analysis considering temporal supply voltage fluctuation. ASP-DAC 2005: 1098-1101

Hitoshi Nakakubo, Takashi Sato: Static and Dynamic Scoring by Web Page Grouping. ICDE Workshops 2005: 1258

Natsuki Yamanobe, Hiromitsu Fujii, Yusuke Maeda, Tamio Arai, Atsushi Watanabe, Tetsuaki Kato, Takashi Sato, Kokoro Hatanaka: Optimization of damping control parameters for cycle time reduction in clutch assembly. IROS 2005: 3251-3256

Kan Takeuchi, Kazumasa Yanagisawa, Takashi Sato, Kazuko Sakamoto, Saburo Hojo: Probabilistic crosstalk delay estimation for ASICs. IEEE Trans. on CAD of Integrated Circuits and Systems 23(9): 1377-1383 (2004)

Natsuki Yamanobe, Yusuke Maeda, Tamio Arai, Tetsuaki Kato, Takashi Sato, Kokoro Hatanaka: Design of damping control parameters for peg-in-hole by industrial manipulator considering cycle time. IROS 2004: 3351-3356

Takashi Sato, Takashi Hashimoto: Dynamic Social Simulation with Multi-agents Having Internal Dynamics. JSAI Workshops 2004: 237-251

Takashi Sato, Yu Cao, Kanak Agarwal, Dennis Sylvester, Chenming Hu: Bidirectional closed-form transformation between on-chip coupling noise waveforms and interconnect delay-change curves. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 560-572 (2003)

Atsushi Kurokawa, Takashi Sato, Hiroo Masuda: Approximate formulae approach for efficient inductance extraction. ASP-DAC 2003: 143-148

Takashi Sato, Toshiki Kanamoto, Atsushi Kurokawa, Yoshiyuki Kawakami, Hiroki Oka, Tomoyasu Kitaura, Hiroyuki Kobayashi, Masanori Hashimoto: Accurate prediction of the impact of on-chip inductance on interconnect delay using electrical and physical parameter-based RSF. ASP-DAC 2003: 149-155

Takashi Sato, Hiroo Masuda: Design and Measurement of an Inductance-Oscillator for Analyzing Inductance Impact on On-Chip Interconnect Delay. ISQED 2003: 395-400

Kanak Agarwal, Yu Cao, Takashi Sato, Dennis Sylvester, Chenming Hu: Efficient Generation of Delay Change Curves for Noise-Aware Static Timing Analysis. VLSI Design 2002: 77-

Takashi Sato, Eiji Yoshida, Yasunori Kakebayashi, Joji Asakura, Norihisa Komoda: Application of IEC61131-3 for semiconductor processing equipment. ETFA (2) 2001: 47-50

Takashi Sato: ChangFast Arbitrary String Search from Large Data. CODAS 1996: 530-537

Takashi Sato: Fast Full Text Search Using Tree Structured[TS] File. Stringology 1996: 42-63

Jun-Ichi Aoe, Katsushi Morimoto, Takashi Sato: An Efficient Implementation of Trie Structures. Softw., Pract. Exper. 22(9): 695-721 (1992)

Takashi Sato: Order preserving code having a search tree. Systems and Computers in Japan 22(9): 23-32 (1991)

Takao Tsuda, Takashi Sato: Transposition of Large Tabular Data Structures with Applications to Physical Database Organization. Acta Inf. 19: 13-33 (1983)

Takao Tsuda, Akira Urano, Takashi Sato: Transposition of Large Tabular Data Structures with Applications to Physical Database Organization. Acta Inf. 19: 167-182 (1983)

Takao Tsuda, Takashi Sato, Takaaki Tatsumi: Generalization of Floyd's Model on Permuting Information in Idealized Two-Level Storage. Inf. Process. Lett. 16(4): 183-188 (1983)

Tsutomu Hoshino, Toshio Kawai, Tomonori Shirakawa, Junichi Higashino, Akira Yamaoka, Hachidai Ito, Takashi Sato, Kazuo Sawada: PACS: A Parallel Microprocessor Array for Scientific Calculations. ACM Trans. Comput. Syst. 1(3): 195-221 (1983)

Fumihiko Mori, Hiroshi Tsuji, Takashi Sato: A conversational decision support system for resource allocation without explicit objective function. AFIPS National Computer Conference 1980: 1-6