Toshinori Sato

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura, Takanori Hayashida: A Selective Replacement Method for Timing-Error-Predicting flip-Flops. Journal of Circuits, Systems, and Computers 21(6) (2012)

Toshinori Sato, Hideki Mori, Rikiya Yano, Takanori Hayashida: Importance of Single-Core Performance in the Multicore Era. ACSC 2012: 107-114

Alex Veidenbaum, Nectarios Koziris, Toshinori Sato, Avi Mendelson: Topic 4: High-Performance Architecture and Compilers. Euro-Par 2012: 204-205

Toshinori Sato, Takanori Hayashida, Ken Yano: Dynamically reducing overestimated design margin of MultiCores. HPCS 2012: 403-409

Ken Yano, Takanori Hayashida, Toshinori Sato: Analysis of SER Improvement by Radiation Hardened Latches. PRDC 2012: 89-95

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura: Short Term Cell-Flipping Technique for Mitigating SNM Degradation Due to NBTI. IEICE Transactions 94-C(4): 520-529 (2011)

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura: Signal probability control for relieving NBTI in SRAM cells. ISQED 2010: 660-666

Yuji Kunitake, Toshinori Sato, Hiroto Yasuura: A Replacement Strategy for Canary Flip-Flops. PRDC 2010: 227-228

Yuji Kunitake, Kazuhiro Mima, Toshinori Sato, Hiroto Yasuura: Enhancements of a Circuit-Level Timing Speculation Technique and Their Evaluations Using a Co-simulation Environment. IEICE Transactions 92-C(4): 483-491 (2009)

Shingo Watanabe, Masanori Hashimoto, Toshinori Sato: A case for exploiting complex arithmetic circuits towards performance yield enhancement. ISQED 2009: 401-407

Toshinori Sato, Shingo Watanabe: Uncriticality-directed scheduling for tackling variation and power challenges. ISQED 2009: 820-825

Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato: A Low-Power Instruction Issue Queue for Microprocessors. IEICE Transactions 91-C(4): 400-409 (2008)

Toshinori Sato: A Simple Mechanism for Collapsing Instructions under Timing Speculation. IEICE Transactions 91-C(9): 1394-1401 (2008)

Toshinori Sato, Toshimasa Funaki: Dependability, power, and performance trade-off on a multicore processor. ASP-DAC 2008: 714-719

Toshimasa Funaki, Toshinori Sato: Formulating MITF for a Multicore Processor with SEU Tolerance. DSD 2008: 234-241

Toshinori Sato, Shingo Watanabe: Instruction Scheduling for Variation-Originated Variable Latencies. ISQED 2008: 361-364

Shingo Watanabe, Toshinori Sato: Uncriticality-Directed Low-Power Instruction Scheduling. ISVLSI 2008: 69-74

Tohru Ishihara, Seiichiro Yamaguchi, Yuriko Ishitobi, Tadayuki Matsumura, Yuji Kunitake, Yuichiro Oyama, Yusuke Kaneda, Masanori Muroyama, Toshinori Sato: AMPLE: An Adaptive Multi-Performance Processor for Low-Energy Embedded Applications. SASP 2008: 83-88

Jesús Labarta, Kazuki Joe, Toshinori Sato (Eds.): High-Performance Computing - 6th International Symposium, ISHPC 2005, Nara, Japan, September 7-9, 2005, First International Workshop on Advanced Low Power Systems, ALPS 2006, Revised Selected Papers. Lecture Notes in Computer Science 4759, Springer 2008, isbn 978-3-540-77703-8

Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu: Realizing Energy-Efficient MultiCore Processors by Utilizing Speculative Thread-Level Parallelism. I. J. Comput. Appl. 14(2): 79-91 (2007)

Kenji Kise, Toshinori Sato, Hironori Nakajo: Introduction. SIGARCH Computer Architecture News 35(5): 1-2 (2007)

Shingo Watanabe, Akihiro Chiyonobu, Toshinori Sato: Indirect Tag Search Mechanism for Instruction Window Energy Reduction. CIT 2007: 841-846

Yuji Kunitake, Akihiro Chiyonobu, Koichiro Tanaka, Toshinori Sato: Challenges in Evaluations for a Typical-Case Design Methodology. ISQED 2007: 374-379

Toshinori Sato, Yuji Kunitake: A Simple Flip-Flop Circuit for Typical-Case Designs for DFM. ISQED 2007: 539-544

Toshinori Sato, Yuji Kunitake: Exploiting Input Variations for Energy Reduction. PATMOS 2007: 384-393

Toshinori Sato, Toshimasa Funaki: Power-Performance Trade-Off of a Dependable Multicore Processor. PRDC 2007: 268-273

Seiichiri Fujii, Akihito Sakanaka, Akihiro Chiyonobu, Toshinori Sato: A leakage-energy-reduction technique for cache memories in embedded processors. J. Embedded Computing 2(1): 49-55 (2006)

Akihiro Chiyonobu, Toshinori Sato: Energy-efficient instruction scheduling utilizing cache miss information. SIGARCH Computer Architecture News 34(1): 65-70 (2006)

Toshinori Sato, Yuu Tanaka, Hidenori Sato, Toshimasa Funaki, Takenori Koushiro, Akihiro Chiyonobu: Improving Energy Efficiency Via Speculative Multithreading on MultiCore Processors. PATMOS 2006: 553-562

Toshinori Sato, Akihiro Chiyonobu: Evaluating the Impact of Fault Recovery on Superscalar Processor Performance. PRDC 2006: 369-370

Toshinori Sato, Akihiro Chiyonobu: An Energy-Efficient Clustered Superscalar Processor. IEICE Transactions 88-C(4): 544-551 (2005)

Toshinori Sato: Exploiting Trivial Computation in Dependable Processors. Computers and Their Applications 2005: 168-173

Yuichiro Imaizumi, Toshinori Sato: Folding Active List for High Performance and Low Power. ISHPC 2005: 33-42

Takamasa Tokunaga, Toshinori Sato: Profiling with Helper Threads. Parallel and Distributed Computing and Networks 2005: 1-6

Akihito Sakanaka, Seiichirou Fujii, Toshinori Sato: A leakage-energy-reduction technique for highly-associative caches in embedded systems. SIGARCH Computer Architecture News 32(3): 50-54 (2004)

Hidenori Sato, Toshinori Sato: A static and dynamic energy reduction technique for I-cache and BTB in embedded processors. ASP-DAC 2004: 830-833

Seiichiro Fujii, Toshinori Sato: Non-uniform Set-Associative Caches for Power-Aware Embedded Processors. EUC 2004: 217-226

Masaharu Goto, Toshinori Sato: Leakage Energy Reduction in Register Renaming. ICDCS Workshops 2004: 890-895

Akihiro Chiyonobu, Toshinori Sato: Investigating heterogeneous combination of functional units for a criticality-based low-power processor architecture. ISICT 2004: 190-195

Yuu Tanaka, Toshinori Sato, Takenori Koushiro: The potential in energy efficiency of a speculative chip-multiprocessor. SPAA 2004: 273-274

Toshinori Sato, Itsujiro Arita: Combining variable latency pipeline with instruction reuse for execution latency reduction. Systems and Computers in Japan 34(12): 11-21 (2003)

Takenori Koushiro, Toshinori Sato, Itsujiro Arita: A trace-level value predictor for Contrail processors. SIGARCH Computer Architecture News 31(3): 42-47 (2003)

Asami Tanino, Toshinori Sato: Simplifying High-Frequency Microprocessor Design via Timing Constraint Speculation. CAINE 2003: 282-287

Toshinori Sato: Exploiting Instruction Redundancy for Transient Fault Tolerance. DFT 2003: 547-554

Toshinori Sato, Daisuke Morishita: A field-customizable and runtime-adaptable microarchitecture. FPT 2003: 328-331

Akihito Sakanaka, Toshinori Sato: Reducing Static Energy of Cache Memories via Prediction-Table-Less Way Prediction. PATMOS 2003: 530-539

Toshinori Sato, Kiichi Sugitani, Akihiko Hamano: Evaluating Influence of Compiler Optimizations on Data Speculation. J. Inf. Sci. Eng. 18(6): 1027-1036 (2002)

Toshinori Sato: Evaluating the impact of reissued instructions on data speculative processor performance. Microprocessors and Microsystems 25(9-10): 469-482 (2002)

Toshinori Sato, Itsujiro Arita: Simplifying Instruction Issue Logic in Superscalar Processors. DSD 2002: 341-346

Toshinori Sato, Itsujiro Arita: Low-Cost Value Predictors Using Frequent Value Locality. ISHPC 2002: 106-119

Toshinori Sato, Itsujiro Arita: Reducing Energy Consumption via Low-Cost Value Prediction. PATMOS 2002: 380-389

Toshiyuki Yamamoto, Kou Morita, Toshinori Sato, Itsujiro Arita: The KIT COSMOS Processor: An Application of Multi-Threading for Dynamic Optimization. PDPTA 2002: 1010-1016

Toshinori Sato, Itsujiro Arita: Tolerating Transient Faults through an Instruction Reissue Mechanism. ISCA PDCS 2001: 240-247

Toshinori Sato, Itsujiro Arita: Execution Latency Reduction via Variable Latency Pipeline and Instruction Reuse. Euro-Par 2001: 428-438

Toshinori Sato, Akihiko Hamano, Kiichi Sugitani, Itsujiro Arita: Influence of Compiler Optimizations on Value Prediction. HPCN Europe 2001: 312-321

Toshinori Sato, Itsujiro Arita: In Search of Efficient Reliable Processor Design. ICPP 2001: 525-532

Toshinori Sato, Itsujiro Arita: Evaluating Low-Cost Fault-Tolerance Mechanism for Microprocessors on Multimedia Applications. PRDC 2001: 225-232

Toshinori Sato: Quantitative evaluation of pipelining and decoupling a dynamic instruction scheduling mechanism. Journal of Systems Architecture 46(13): 1231-1252 (2000)

Atsushi Kunimatsu, Nobuhiro Ide, Toshinori Sato, Yukio Endo, Hiroaki Murakami, Takayuki Kamei, Masashi Hirano, Fujio Ishihara, Haruyuki Tago, Masaaki Oka, Akio Ohba, Teiji Yutaka, Toyoshi Okada, Masakazu Suzuoki: Vector Unit Architecture for Emotion Synthesis. IEEE Micro 20(2): 40-47 (2000)

Takayuki Kamei, Hideaki Takeda, Yukio Ootaguro, Takayoshi Shimazawa, Kazuhiko Tachibana, Shin'ichi Kawakami, Seiji Norimatsu, Fujio Ishihara, Toshinori Sato, Hiroaki Murakami, Nobuhiro Ide, Yukio Endo, Akira Aono, Atsushi Kunimatsu: 300MHz design methodology of VU for emotion synthesis. ASP-DAC 2000: 635-640

Toshinori Sato, Itsujiro Arita: Partial Resolution in Data Value Predictors. ICPP 2000: 69-76

Toshinori Sato, Itsujiro Arita: Table size reduction for data value predictors by exploiting narrow width values. ICS 2000: 196-205

Toshinori Sato, Itsujiro Arita: Comprehensive Evaluation of an Instruction Reissue Mechanism. ISPAN 2000: 78-87

Toshinori Sato, Itsujiro Arita: The KIT COSMOS Processor: Introducing CONDOR. PDPTA 2000

Toshinori Sato: A Simulation Study of Combining Load Value and Address Predictors. International Journal of High Speed Computing 10(3): 301-325 (1999)

Toshinori Sato: A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism. EUROMICRO 1999: 1178-1185

Toshinori Sato: Decoupling Recovery Mechanism for Data Speculation from Dynamic Instruction Scheduling Structure. Euro-Par 1999: 1281-1290

Toshinori Sato: Profile-Based Selection of Load Value and Address Predictors. ISHPC 1999: 17-28

Toshinori Sato: Data Dependence Speculation Using Data Address Prediction and its Enhancement with Instruction Reissue. EUROMICRO 1998: 10285-10292

Toshinori Sato: Data Dependence Path Reductio with Tunneling Load Instructions. ISHPC 1997: 119-130