Akashi Satoh

Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh: A Configurable On-Chip Glitchy-Clock Generator for Fault Injection Experiments. IEICE Transactions 95-A(1): 263-266 (2012)

Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takeshi Sugawara, Yoshiki Kayano, Takafumi Aoki, Shigeki Minegishi, Akashi Satoh, Hideaki Sone, Hiroshi Inoue: Evaluation of Information Leakage from Cryptographic Hardware via Common-Mode Current. IEICE Transactions 95-C(6): 1089-1097 (2012)

Miroslav Knezevic, Kazuyuki Kobayashi, Jun Ikegami, Shin'ichiro Matsuo, Akashi Satoh, Ünal Koçabas, Junfeng Fan, Toshihiro Katashita, Takeshi Sugawara, Kazuo Sakiyama, Ingrid Verbauwhede, Kazuo Ohta, Naofumi Homma, Takafumi Aoki: Fair and Consistent Hardware Evaluation of Fourteen Round Two SHA-3 Candidates. IEEE Trans. VLSI Syst. 20(5): 827-840 (2012)

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh: High-Performance Architecture for Concurrent Error Detection for AES Processors. IEICE Transactions 94-A(10): 1971-1980 (2011)

Sho Endo, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh: An on-chip glitchy-clock generator for testing fault injection attacks. J. Cryptographic Engineering 1(4): 265-270 (2011)

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: Systematic Design of RSA Processors Based on High-Radix Montgomery Multipliers. IEEE Trans. VLSI Syst. 19(7): 1136-1146 (2011)

Daisuke Fujimoto, Makoto Nagata, Toshihiro Katashita, Akihiro T. Sasaki, Yohei Hori, Akashi Satoh: A fast power current analysis methodology using capacitor charging model for side channel attack evaluation. HOST 2011: 87-92

Yohei Hori, Hyunho Kang, Toshihiro Katashita, Akashi Satoh: Pseudo-LFSR PUF: A Compact, Efficient and Reliable Physical Unclonable Function. ReConFig 2011: 223-228

Daisuke Suzuki, Minoru Saeki, Koichi Shimizu, Akashi Satoh, Tsutomu Matsumoto: A Design Methodology for a DPA-Resistant Circuit with RSL Techniques. IEICE Transactions 93-A(12): 2497-2508 (2010)

Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir: Comparative Power Analysis of Modular Exponentiation Algorithms. IEEE Trans. Computers 59(6): 795-807 (2010)

Kazuyuki Kobayashi, Jun Ikegami, Kazuo Sakiyama, Kazuo Ohta, Miroslav Knezevic, Ünal Koçabas, Junfeng Fan, Ingrid Verbauwhede, Eric Xu Guo, Shin'ichiro Matsuo, Sinan Huang, Leyla Nazhandali, Akashi Satoh: Prototyping Platform for Performance Evaluation of SHA-3 Candidates. HOST 2010: 60-63

Akashi Satoh, Toshihiro Katashita, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki: Hardware Implementations of Hash Function Luffa. HOST 2010: 130-134

Yohei Hori, Takahiro Yoshida, Toshihiro Katashita, Akashi Satoh: Quantitative and Statistical Performance Evaluation of Arbiter Physical Unclonable Functions on FPGAs. ReConFig 2010: 298-303

Akashi Satoh, Takeshi Sugawara, Takafumi Aoki: High-Performance Hardware Architectures for Galois Counter Mode. IEEE Trans. Computers 58(7): 917-930 (2009)

Minoru Saeki, Daisuke Suzuki, Koichi Shimizu, Akashi Satoh: A Design Methodology for a DPA-Resistant Cryptographic LSI with RSL Techniques. CHES 2009: 189-204

Akashi Satoh, Nicolas Sklavos: Compact and High-speed Hardware Architectures for Hash Function Tiger. ISCAS 2009: 1401-1404

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: Evaluation of Simple/Comparative Power Analysis against an RSA ASIC Implementation. ISCAS 2009: 2918-2921

Yingxi Lu, Keanhong Boey, Máire O'Neill, John V. McCanny, Akashi Satoh: Is the differential frequency-based attack effective against random delay insertion? SiPS 2009: 051-056

Takeshi Sugawara, Yu-ichi Hayashi, Naofumi Homma, Takaaki Mizuki, Takafumi Aoki, Hideaki Sone, Akashi Satoh: Mechanism behind Information Leakage in Electromagnetic Analysis of Cryptographic Modules. WISA 2009: 66-78

Naofumi Homma, Sei Nagashima, Takeshi Sugawara, Takafumi Aoki, Akashi Satoh: A High-Resolution Phase-Based Waveform Matching and Its Application to Side-Channel Attacks. IEICE Transactions 91-A(1): 193-202 (2008)

Naofumi Homma, Atsushi Miyamoto, Takafumi Aoki, Akashi Satoh, Adi Shamir: Collision-Based Power Analysis of Modular Exponentiation Using Chosen-Message Pairs. CHES 2008: 15-29

Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki: High-Performance Concurrent Error Detection Scheme for AES Hardware. CHES 2008: 100-112

Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda: Bitstream encryption and authentication with AES-GCM in dynamically reconfigurable systems. FPL 2008: 23-28

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: Chosen-message SPA attacks against FPGA-based RSA hardware implementations. FPL 2008: 35-40

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: Systematic design of high-radix Montgomery multipliers for RSA processors. ICCD 2008: 416-421

Akashi Satoh: ASIC hardware implementations for 512-bit hash function Whirlpool. ISCAS 2008: 2917-2920

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh: High-performance ASIC implementations of the 128-bit block cipher CLEFIA. ISCAS 2008: 2925-2928

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: Enhanced power analysis attack using chosen message against RSA hardware implementations. ISCAS 2008: 3282-3285

Yohei Hori, Akashi Satoh, Hirofumi Sakane, Kenji Toda: Bitstream Encryption and Authentication Using AES-GCM in Dynamically Reconfigurable Systems. IWSEC 2008: 261-278

Toshihiro Katashita, Akashi Satoh, Takeshi Sugawara, Naofumi Homma, Takafumi Aoki: Enhanced Correlation Power Analysis Using Key Screening Technique. ReConFig 2008: 403-408

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh: Compact ASIC Architectures for the 512-Bit Hash Function Whirlpool. WISA 2008: 28-40

Akashi Satoh, Tadanobu Inoue: ASIC-hardware-focused comparison for hash functions MD5, RIPEMD-160, and SHS. Integration 40(1): 3-10 (2007)

Sei Nagashima, Naofumi Homma, Yuichi Imai, Takafumi Aoki, Akashi Satoh: DPA Using Phase-Based Waveform Matching against Random-Delay Countermeasure. ISCAS 2007: 1807-1810

Atsushi Miyamoto, Naofumi Homma, Takafumi Aoki, Akashi Satoh: SPA against an FPGA-Based RSA Implementation with a High-Radix Montgomery Multiplier. ISCAS 2007: 1847-1850

Takeshi Sugawara, Naofumi Homma, Takafumi Aoki, Akashi Satoh: A High-Performance ASIC Implementation of the 64-bit Block Cipher CAST-128. ISCAS 2007: 1859-1862

Akashi Satoh: High-Speed Parallel Hardware Architecture for Galois Counter Mode. ISCAS 2007: 1863-1866

Akashi Satoh, Takeshi Sugawara, Takafumi Aoki: High-Speed Pipelined Hardware Architecture for Galois Counter Mode. ISC 2007: 118-129

Naofumi Homma, Sei Nagashima, Yuichi Imai, Takafumi Aoki, Akashi Satoh: High-Resolution Side-Channel Attack Using Phase-Based Waveform Matching. CHES 2006: 187-200

Akashi Satoh: Hardware Architecture and Cost Estimates for Breaking SHA-1. ISC 2005: 259-273

Akashi Satoh, Tadanobu Inoue: ASIC-Hardware-Focused Comparison for Hash Functions MD5, RIPEMD-160, and SHS. ITCC (1) 2005: 532-537

Shigenori Shimizu, Hiroshi Ishikawa, Akashi Satoh, Toru Aihara: On-demand design service innovations. IBM Journal of Research and Development 48(5-6): 751-766 (2004)

Sumio Morioka, Akashi Satoh: A 10-Gbps full-AES crypto design with a twisted BDD S-Box architecture. IEEE Trans. VLSI Syst. 12(7): 686-691 (2004)

Akashi Satoh, Kohji Takano: A Scalable Dual-Field Elliptic Curve Cryptographic Processor. IEEE Trans. Computers 52(4): 449-460 (2003)

Akashi Satoh, Sumio Morioka: Unified Hardware Architecture for 128-Bit Block Ciphers AES and Camellia. CHES 2003: 304-318

Akashi Satoh, Sumio Morioka: Hardware-Focused Performance Comparison for the Standard Block Ciphers AES, Camellia, and Triple-DES. ISC 2003: 252-266

Sumio Morioka, Akashi Satoh: An Optimized S-Box Circuit Architecture for Low Power AES Design. CHES 2002: 172-186

Sumio Morioka, Akashi Satoh: A 10 Gbps Full-AES Crypto Design with a Twisted-BDD S-Box Architecture. ICCD 2002: 98-103

Akashi Satoh, Sumio Morioka: Small and High-Speed Hardware Architectures for the 3GPP Standard Cipher KASUMI. ISC 2002: 48-62

Akashi Satoh, Sumio Morioka, Kohji Takano, Seiji Munetoh: A Compact Rijndael Hardware Architecture with S-Box Optimization. ASIACRYPT 2001: 239-254

Akashi Satoh, Nobuyuki Ooba, Kohji Takano, Edward D'Avignon: High-Speed MARS Hardware. AES Candidate Conference 2000: 305-316

W. K. Luk, Yasunao Katayama, Wei Hwang, Matthew R. Wordeman, T. Kirihata, Akashi Satoh, Seiji Munetoh, H. Wong, B. El-Kareh, P. Xiao, Rajiv V. Joshi: Development of a High Bandwidth Merged Logic/DRAM Multimedia Chip. ICCD 1997: 279-285

Akashi Satoh, Y. Kobayashi, H. Niijima, Nobuyuki Ooba, Seiji Munetoh, S. Sone: A High-Speed Small RSA Encryption LSI with Low Power Dissipation. ISW 1997: 174-187