Prashant Saxena

Tong Gao, Prashant Saxena: On pioneering nanometer-era routing problems. ISPD 2012: 65-68

Prashant Saxena, Yao-Wen Chang: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 30(2): 165-166 (2011)

Stephen M. Plaza, Prashant Saxena, Thomas R. Shiple, Pei-Hsin Ho: Multi-mode redundancy removal. ISQED 2011: 791-799

Gi-Joon Nam, Prashant Saxena: Guest Editorial. IEEE Trans. on CAD of Integrated Circuits and Systems 29(2): 169-170 (2010)

Prashant Saxena, Yao-Wen Chang (Eds.): Proceedings of the 2010 International Symposium on Physical Design, ISPD 2010, San Francisco, California, USA, March 14-17, 2010. ACM 2010, isbn 978-1-60558-920-6

Prashant Saxena, Vishal Khandelwal, Changge Qiao, Pei-Hsin Ho, J.-C. Lin, Mahesh A. Iyer: On improving optimization effectiveness in interconnect-driven physical synthesis. ISPD 2009: 51-58

Gi-Joon Nam, Prashant Saxena (Eds.): Proceedings of the 2009 International Symposium on Physical Design, ISPD 2009, San Diego, California, USA, March 29 - April 1, 2009. ACM 2009, isbn 978-1-60558-449-2

Prashant Saxena, Rupesh S. Shelar, Sachin S. Sapatnekar: Routing Congestion in VLSI Circuits - Estimation and Optimization. Series on integrated circuits and systems, Springer 2007, isbn 978-0-387-30037-5, pp. I-XIV, 1-248

Rupesh S. Shelar, Prashant Saxena, Sachin S. Sapatnekar: Technology Mapping Algorithm Targeting Routing Congestion Under Delay Constraints. IEEE Trans. on CAD of Integrated Circuits and Systems 25(4): 625-636 (2006)

Prashant Saxena: On controlling perturbation due to repeaters during quadratic placement. IEEE Trans. on CAD of Integrated Circuits and Systems 25(9): 1733-1743 (2006)

Prashant Saxena: The scaling of interconnect buffer needs. SLIP 2006: 109-112

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric with application to technology mapping. IEEE Trans. on CAD of Integrated Circuits and Systems 24(5): 696-710 (2005)

Prashant Saxena, Kumar N. Lalgudi, Hans J. Greub, Janet Meiling Wang Roveda: A perturbation-aware noise convergence methodology for high frequency microprocessors. ASP-DAC 2005: 717-722

Brent Goplen, Prashant Saxena, Sachin S. Sapatnekar: Net weighting to reduce repeater counts during placement. DAC 2005: 503-508

Zhuoyuan Li, Xianlong Hong, Qiang Zhou, Yici Cai, Jinian Bian, Hannal Yang, Prashant Saxena, Vijay Pitchumani: A divide-and-conquer 2.5-D floorplanning algorithm based on statistical wirelength estimation. ISCAS (6) 2005: 6230-6233

Rupesh S. Shelar, Prashant Saxena, Xinning Wang, Sachin S. Sapatnekar: An efficient technology mapping algorithm targeting routing congestion under delay constraints. ISPD 2005: 137-144

Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick: Repeater scaling and its impact on CAD. IEEE Trans. on CAD of Integrated Circuits and Systems 23(4): 451-463 (2004)

Janet Meiling Wang, Prashant Saxena, Omar Hafiz, Xing Wang: Realizable parasitic reduction for distributed interconnects using matrix pencil technique. ASP-DAC 2004: 780-785

Prashant Saxena, Bill Halpin: Modeling repeaters explicitly within analytical placement. DAC 2004: 699-704

Desmond Kirkpatrick, Peter J. Osler, Louis Scheffer, Prashant Saxena, Dennis Sylvester: The great interconnect buffering debate: are you a chicken or an ostrich? ISPD 2004: 61

Rupesh S. Shelar, Sachin S. Sapatnekar, Prashant Saxena, Xinning Wang: A predictive distributed congestion metric and its application to technology mapping. ISPD 2004: 210-217

Prashant Saxena, Satyanarayan Gupta: On integrating power and signal routing for shield count minimization in congested regions. IEEE Trans. on CAD of Integrated Circuits and Systems 22(4): 437-445 (2003)

Ki-Wook Kim, Seong-Ook Jung, Taewhan Kim, Prashant Saxena, C. L. Liu, S.-M. S. Kang: Coupling delay optimization by temporal decorrelation using dual threshold voltage technique. IEEE Trans. VLSI Syst. 11(5): 879-887 (2003)

Prashant Saxena, Noel Menezes, Pasquale Cocchini, Desmond Kirkpatrick: The scaling challenge: can correct-by-construction design help? ISPD 2003: 51-58

B. Chappell, X. Wang, P. Patra, Prashant Saxena, J. Vendrell, Satyanarayan Gupta, S. Varadarajan, W. Gomes, S. Hussain, H. Krishnamurthy, M. Venkateshmurthy, S. Jain: A System-Level Solution to Domino Synthesis with 2 GHz Application. ICCD 2002: 164-

Prashant Saxena, Satyanarayan Gupta: Shield count minimization in congested regions. ISPD 2002: 78-83

Prashant Saxena, C. L. Liu: Optimization of the maximum delay of global interconnects duringlayer assignment. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 503-515 (2001)

Ki-Wook Kim, Seong-Ook Jung, Prashant Saxena, C. L. Liu, Sung-Mo Kang: Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique. DAC 2001: 732-737

Prashant Saxena, C. L. Liu: A postprocessing algorithm for crosstalk-driven wire perturbation. IEEE Trans. on CAD of Integrated Circuits and Systems 19(6): 691-702 (2000)

Prashant Saxena, C. L. Liu: Crosstalk Minimization Using Wire Perturbations. DAC 1999: 100-103

Prashant Saxena, Peichen Pan, C. L. Liu: The Retiming of Single-Phase Clocked Circuits Containing Level-Sensitive Latches. VLSI Design 1999: 402-407

Prashant Saxena, C. L. Liu: A performance-driven layer assignment algorithm for multiple interconnect trees. ICCAD 1998: 124-127

Vamsi Boppana, Prashant Saxena, Prithviraj Banerjee, W. Kent Fuchs, C. L. Liu: A Parallel Algorithm for the Technology Mapping of LUT-Based FPGAs. Euro-Par, Vol. I 1996: 828-831

Aviezri S. Fraenkel, Edward M. Reingold, Prashant Saxena: Efficient Management of Dynamic Tables. Inf. Process. Lett. 50(1): 25-30 (1994)