René Schüffny

Sebastian Höppner, Holger Eisenreich, Stephan Henker, Dennis Walter, Georg Ellguth, René Schüffny: A Compact Clock Generator for Heterogeneous GALS MPSoCs in 65-nm CMOS Technology. IEEE Trans. VLSI Syst. 21(3): 566-570 (2013)

Johannes Partzsch, René Schüffny: Developing structural constraints on connectivity for biologically embedded neural networks. Biological Cybernetics 106(3): 191-200 (2012)

Sebastian Höppner, Dennis Walter, Georg Ellguth, René Schüffny: On-Chip Measurement and Compensation of Timing Imbalances in High-Speed Serial NoC Links. IJERTCS 3(4): 42-56 (2012)

Stefan Scholze, Holger Eisenreich, Sebastian Höppner, Georg Ellguth, Stephan Henker, Mario Ander, Stefan Hänzsche, Johannes Partzsch, Christian Mayr, René Schüffny: A 32 GBit/s communication SoC for a waferscale neuromorphic system. Integration 45(1): 61-75 (2012)

Stephan Henker, Johannes Partzsch, René Schüffny: Accuracy evaluation of numerical methods used in state-of-the-art simulators for spiking neural networks. Journal of Computational Neuroscience 32(2): 309-326 (2012)

Sebastian Höppner, Chenming Shao, Holger Eisenreich, Georg Ellguth, Mario Ander, René Schüffny: A power management architecture for fast per-core DVFS in heterogeneous MPSoCs. ISCAS 2012: 261-264

Johannes Schemmel, Andreas Grübl, Stephan Hartmann, Alexander Kononov, Christian Mayr, Karlheinz Meier, Sebastian Millner, Johannes Partzsch, Stefan Schiefer, Stefan Scholze, René Schüffny, Marc-Olivier Schwartz: Live demonstration: A scaled-down version of the BrainScaleS wafer-scale neuromorphic system. ISCAS 2012: 702

Stefan Hänzsche, Stephan Henker, René Schüffny, Thomas Reichel, Matthias Garzarolli: A 14 bit self-calibrating charge redistribution SAR ADC. ISCAS 2012: 1038-1041

Dennis Walter, Sebastian Höppner, Holger Eisenreich, Georg Ellguth, Stephan Henker, Stefan Hänzsche, René Schüffny, Markus Winter, Gerhard Fettweis: A source-synchronous 90Gb/s capacitively driven serial on-chip link over 6mm in 65nm CMOS. ISSCC 2012: 180-182

Markus Winter, Steffen Kunze, Esther P. Adeva, Björn Mennenga, Emil Matús, Gerhard Fettweis, Holger Eisenreich, Georg Ellguth, Sebastian Höppner, Stefan Scholze, René Schüffny, Tomoyoshi Kobori: A 335Mb/s 3.9mm² 65nm CMOS flexible MIMO detection-decoding engine achieving 4G wireless data rates. ISSCC 2012: 216-218

Christian Mayr, Paul Stärke, Johannes Partzsch, René Schüffny, Love Cederstroem, Yao Shuai, Nan Du, Heidemarie Schmidt: Waveform Driven Plasticity in BiFeO3 Memristive Devices: Model and Implementation. NIPS 2012: 1709-1717

Daniel Brüderle, Mihai A. Petrovici, Bernhard Vogginger, Matthias Ehrlich, Thomas Pfeil, Sebastian Millner, Andreas Grübl, Karsten Wendt, Eric Müller, Marc-Olivier Schwartz, Dan Husmann de Oliveira, Sebastian Jeltsch, Johannes Fieres, Moritz Schilling, Paul Müller, Oliver Breitwieser, Venelin Petkov, Lyle Muller, Andrew P. Davison, Pradeep Krishnamurthy, Jens Kremkow, Mikael Lundqvist, Eilif Mueller, Johannes Partzsch, Stefan Scholze, Lukas Zühl, Christian Mayr, Alain Destexhe, Markus Diesmann, Tobias C. Potjans, Anders Lansner, René Schüffny, Johannes Schemmel, Karlheinz Meier: A comprehensive workflow for general-purpose neural modeling with highly configurable neuromorphic hardware systems. Biological Cybernetics 104(4-5): 263-296 (2011)

Johannes Partzsch, René Schüffny: Analyzing the Scaling of Connectivity in Neuromorphic Hardware and in Models of Neural Networks. IEEE Transactions on Neural Networks 22(6): 919-935 (2011)

Marko Noack, Christian Mayr, Johannes Partzsch, René Schüffny: Synapse dynamics in CMOS derived from a model of neurotransmitter release. ECCTD 2011: 198-201

Stefan Schiefer, Stephan Hartmann, Stefan Scholze, Johannes Partzsch, Christian Mayr, Stephan Henker, René Schüffny: Live demonstration: Packet-based AER with 3Gevent/s cumulative throughput. ISCAS 2011: 1988

Karsten Wendt, Matthias Ehrlich, René Schüffny: GMPath - A Path Language for Navigation, Information Query and Modification of Data Graphs. ANNIIP 2010: 33-42

Matthias Ehrlich, Karsten Wendt, Lukas Zühl, René Schüffny, Daniel Brüderle, Eric Müller, Bernhard Vogginger: A Software Framework for Mapping Neural Networks to a Wafer-scale Neuromorphic Hardware System. ANNIIP 2010: 43-52

Christian Mayr, Johannes Partzsch, René Schüffny: A critique of BCM behavior verification for STDP-type plasticity models. ESANN 2010

Stephan Hartmann, Stefan Schiefer, Stefan Scholze, Johannes Partzsch, Christian Mayr, Stephan Henker, René Schüffny: Highly integrated packet-based AER communication infrastructure with 3Gevent/S throughput. ICECS 2010: 950-953

Christian Mayr, Marko Noack, Johannes Partzsch, René Schüffny: Replicating experimental spike and rate based neural learning in CMOS. ISCAS 2010: 105-108

Johannes Uhlig, Sebastian Höppner, Georg Ellguth, René Schüffny: A low-power cell-based-design multi-port register file in 65nm CMOS technology. ISCAS 2010: 313-316

Sebastian Höppner, René Schüffny, Zuo-Min Tsai, Huei Wang: Wide swing signal amplification by SC voltage doubling. ISCAS 2010: 761-764

Christian Mayr, Johannes Partzsch, René Schüffny: On the Relation between Bursts and Dynamic Synapse Properties: A Modulation-Based Ansatz. Comp. Int. and Neurosc. 2009 (2009)

Christian Mayr, Johannes Partzsch, René Schüffny: Transient responses of activity-dependent synapses to modulated pulse trains. Neurocomputing 73(1-3): 99-105 (2009)

Holger Eisenreich, Christian Mayr, Stephan Henker, Michael Wickert, René Schüffny: A novel ADPLL design using successive approximation frequency control. Microelectronics Journal 40(11): 1613-1622 (2009)

Johannes Partzsch, René Schüffny: On the routing complexity of neural network models - Rent's Rule revisited. ESANN 2009

Georg Ellguth, Stephan Henker, Christian Mayr, René Schüffny: Current conveyor based amplifier and adaptive buffer for use in an analog frontend. ICECS 2009: 9-12

Johannes Uhlig, René Schüffny, Harald Neubauer, Johann Hauer, Joachim Haase: A low-power continuous-time incremental 2nd-order-MASH ΣΔ-modulator for a CMOS imager. ICECS 2009: 33-36

Johannes Partzsch, Christian Mayr, René Schüffny: BCM and Membrane Potential: Alternative Ways to Timing Dependent Plasticity. ICONIP (1) 2008: 137-144

Christian Mayr, Arne Heittmann, René Schüffny: Gabor-Like Image Filtering Using a Neural Microcircuit. IEEE Transactions on Neural Networks 18(3): 955-959 (2007)

Christian Mayr, René Schüffny: Neighborhood Rank Order Coding for Robust Texture Analysis and Feature Extraction. HIS 2007: 290-301

Christian Mayr, René Schüffny: Applying Spiking Neural Nets to Noise Shaping. IEICE Transactions 88-D(8): 1885-1892 (2005)

Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny: Pulse coupled neural networks with adaptive synapses for image segmentation. ARCS Workshops 2004: 275-282

Jörg Schreiter, Ulrich Ramacher, Arne Heittmann, Daniel Matolin, René Schüffny: Cellular pulse-coupled neural network with adaptive weights for image segmentation and its VLSI implementation. Image Processing: Algorithms and Systems 2004: 290-296

Daniel Matolin, Jörg Schreiter, Stefan Getzlaff, René Schüffny: An Analog VLSI Pulsed Neural Network Implementation for Image Segmentation. PARELEC 2004: 51-55

Martin Franz, René Schüffny: Segmentation of Blood Vessels in Subtraction Angiographic Images. DICTA 2003: 215-224

Stephan Henker, Jens-Uwe Schluessler, René Schüffny: Concept of Color Correction on Multi-Channel CMOS Sensors. DICTA 2003: 771-780

Riad Stefo, Jörg Schreiter, Jens-Uwe Schluessler, René Schüffny: High resolution ADPLL frequency synthesizer for FPGA-and ASIC-based applications. FPT 2003: 28-34

Markus Rullmann, Jens-Uwe Schluessler, René Schüffny: On-chip digital noise reduction for integrated CMOS Cameras. VCIP 2003: 1620-1629

Achim Graupner, M. Tanzer, René Schüffny: CMOS image sensor with shared in-pixel amplifier and calibration facility. APCCAS (2) 2002: 93-96

Arne Heittmann, Ulrich Ramacher, Daniel Matolin, Jörg Schreiter, René Schüffny: An Analog VLSI Pulsed Neural Network for Image Segmentation Using Adaptive Connection Weights. ICANN 2002: 1293-1298

Stefan Getzlaff, Jörg Schreiter, Achim Graupner, René Schüffny: A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing. ISCAS (4) 2001: 486-489

Jörg Krupar, R. Srowik, Jörg Schreiter, Achim Graupner, René Schüffny, U. Jorges: Minimizing charge injection errors in high-precision, high-speed SC-circuits. ISCAS (1) 2001: 727-730

Achim Graupner, Stefan Getzlaff, Jörg Schreiter, René Schüffny: A vision device for image processing. SIP 2001: 78-83

M. Schwarzenberg, M. Traber, M. Scholles, René Schüffny: A VLSI chip for wavelet image compression. ISCAS (4) 1999: 271-274

Jörg Schreiter, R. Srowik, Achim Graupner, Stefan Getzlaff, René Schüffny: Design of parallel preprocessing image sensors. KES 1999: 393-396

Martin Franz, René Schüffny: An Architectural Study of a Massively Parallel Processor for Convolution-Type Operations in Complex Vision Tasks. ICANN 1996: 377-382