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 | 2006 | |
|---|---|---|
| c5 |      | Francisco-Javier Veredas, Michael Scheppler, Hans-Jörg Pfleiderer: Automated conversion from a LUT-based FPGA to a LUT-based MPGA with fast turnaround time. DATE Designers' Forum 2006: 36-41 |
| c4 | | Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer: LUT-based MPGAs for fast turnaround time conversion flow. ISCAS 2006 |
| c3 | | Francisco-Javier Veredas, Michael Scheppler, Bumei Zhai, Hans-Jörg Pfleiderer: Regular Routing Architecture for a LUT-based MPGA. ISVLSI 2006: 257-262 |
| 2005 | ||
| c2 |  | Francisco-Javier Veredas, Michael Scheppler, Will Moffat, Bingfeng Mei: Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. FPL 2005: 106-111 |
| 2003 | ||
| c1 | | Markus Hütter, Holger Bock, Michael Scheppler: A New Reconfigurable Architecture for Single Cycle Context Switching. IPDPS 2003: 186 |
| 1 | Holger Bock | |
| 2 | Markus Hütter | |
| 3 | Bingfeng Mei | |
| 4 | Will Moffat | |
| 5 | Hans-Jörg Pfleiderer | |
| 6 | Francisco-Javier Veredas | |
| 7 | Bumei Zhai |
Colors in the list of coauthors
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