Manfred Schimmler

Christoph Starke, Vasco Grossmann, Lars Wienbrandt, Sven Koschnicke, John Carstens, Manfred Schimmler: Optimizing Investment Strategies with the Reconfigurable Hardware Platform RIVYERA. Int. J. Reconfig. Comp. 2012 (2012)

Christoph Starke, Vasco Grossmann, Lars Wienbrandt, Manfred Schimmler: An FPGA Implementation of an Investment Strategy Processor. Procedia CS 9: 1880-1889 (2012)

Ayman Abbas, Claas Anders Rathje, Lars Wienbrandt, Manfred Schimmler: Dictionary Attack on TrueCrypt with RIVYERA S3-5000. ICPADS 2012: 93-100

Lars Wienbrandt, Daniel Siebert, Manfred Schimmler: Improvement of BLASTp on the FPGA-Based High-Performance Computer RIVYERA. ISBRA 2012: 275-286

Lars Wienbrandt, Stefan Baumgart, Jost Bissel, Florian Schatz, Manfred Schimmler: Massively parallel FPGA-based implementation of BLASTp with the two-hit method. Procedia CS 4: 1967-1976 (2011)

Florian Schatz, Sven Koschnicke, Niklas Paulsen, Christoph Starke, Manfred Schimmler: MPI Performance Analysis of Amazon EC2 Cloud Services for High Performance Computing. ACC (1) 2011: 371-381

Lars Wienbrandt, Stefan Baumgart, Jost Bissel, Carol May Yen Yeo, Manfred Schimmler: Using the reconfigurable massively parallel architecture COPACOBANA 5000 for applications in bioinformatics. Procedia CS 1(1): 1027-1034 (2010)

Lars Wienbrandt, Manfred Schimmler: Collecting Statistical Information in DNA Sequences for the Detection of Special Motifs. BIOCOMP 2010: 274-278

Gerd Pfeiffer, Stefan Baumgart, Jan Schröder, Manfred Schimmler: A Massively Parallel Architecture for Bioinformatics. ICCS (1) 2009: 994-1003

Jan Schröder, Manfred Schimmler, Heiko Schröder, Karsten Tischer: BMA - Boolean Matrices as Model for Motif Kernels. BCBGC 2008: 36-41

Gerd Pfeiffer, Manfred Schimmler: A Specification Methodology for the Optimal Layout of a 2-Stage Interconnect Bus for Massively Parallel Architectures. CDES 2008: 99-104

Tim Güneysu, Christof Paar, Gerd Pfeiffer, Manfred Schimmler: Enhancing COPACOBANA for advanced applications in cryptography and cryptanalysis. FPL 2008: 675-678

Jan Schröder, Lars Wienbrandt, Gerd Pfeiffer, Manfred Schimmler: Massively Parallelized DNA Motif Search on the Reconfigurable Hardware Platform COPACOBANA. PRIB 2008: 436-447

Tim Güneysu, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler, Christian Schleiffer: Parallel Computing with Low-Cost FPGAs: A Framework for COPACOBANA. PARCO 2007: 741-748

Sandeep S. Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler: A Configuration Concept for a Massively Parallel FPGA Architecture. CDES 2006: 207-212

Sandeep S. Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler: Breaking Ciphers with COPACOBANA - A Cost-Optimized Parallel Code Breaker. CHES 2006: 101-118

Sandeep S. Kumar, Christof Paar, Jan Pelzl, Gerd Pfeiffer, Manfred Schimmler: COPACOBANA A Cost-Optimized Special-Purpose Hardware for Code-Breaking. FCCM 2006: 311-312

Stefan Baumgart, Begona Toledo, Karin Spors, Manfred Schimmler: PLUG: An Agent Based Prototype Validation of CAD-Constructions. IKE 2006: 183-190

Viktor Bunimov, Manfred Schimmler: Completely Redundant Modular Exponentiation by Operand Changing. CDES 2005: 224-232

David Narh Amanor, Viktor Bunimov, Christof Paar, Jan Pelzl, Manfred Schimmler: Efficient Hardware Architectures for Modular Multiplication on FPGAs. FPL 2005: 539-542

Gerd Pfeiffer, Heinz Kreft, Manfred Schimmler: Hardware Enhanced Biosequence Alignment. METMBS 2005: 11-17

Manfred Schimmler, Bertil Schmidt, Hans-Werner Lang: A bit-serial floating-point unit for a massively parallel system on a chip. Parallel Algorithms Appl. 19(2-3): 79-95 (2004)

Viktor Bunimov, Manfred Schimmler: High Radix Modular Multiplication of Large Integers Optimised with Respect to Area and Time. ESA/VLSI 2004: 427-433

Manfred Schimmler, Viktor Bunimov: Fast Modular Multiplication by Operand Changing. ITCC (2) 2004: 518-524

Viktor Bunimov, Manfred Schimmler: Area and Time Efficient Modular Multiplication of Large Integers. ASAP 2003: 400-

Viktor Bunimov, Manfred Schimmler, Wolfgang Bziuk: Key Generation for Secure High Speed Communication. Security and Management 2003: 570-576

Viktor Bunimov, Manfred Schimmler: Efficient Parallel Multiplication Algorithm for Large Integres. Euro-Par 2003: 923-928

Manfred Schimmler, Bertil Schmidt, Hans-Werner Lang: Design of a Bit-Serial Floating Point Unit for a Fine Grained Parallel Processor Array. PDPTA 2003: 255-261

Manfred Schimmler, Bertil Schmidt, Hans-Werner Lang, Sven Heithecker: An Area-Efficient Bit-Serial Integer Multiplier. VLSI 2003: 131-137

Manfred Schimmler, Viktor Bunimov: A Simple Circuit to Reduce the Search Range for Large Prime Numbers. VLSI 2003: 285-291

Bertil Schmidt, Heiko Schröder, Manfred Schimmler: A hybrid architecture for bioinformatics. Future Generation Comp. Syst. 18(6): 855-862 (2002)

Bertil Schmidt, Heiko Schröder, Manfred Schimmler: Massively Parallel Solutions for Molecular Sequence Analysis. IPDPS 2002

Bertil Schmidt, Heiko Schröder, Manfred Schimmler: Tomographic Image Reconstruction on the Instruction Systolic Array. Computers and Artificial Intelligence 20(1) (2001)

Bertil Schmidt, Heiko Schröder, Manfred Schimmler: Scanning Biosequence Databases on a Hybrid Parallel Architecture. Euro-Par 2001: 360-370

Bertil Schmidt, Heiko Schröder, Manfred Schimmler: Protein Sequence Comparison on the Instruction Systolic Array. PaCT 2001: 498-509

Bertil Schmidt, Manfred Schimmler: KPROC - An Instruction Systolic Architecture for Parallel Prefix Applications. Scalable Computing: Practice and Experience 3(2) (2000)

Manfred Schimmler: Architectures and Algorithms for Multimedia Applications. Euro-Par 2000: 1085

Bertil Schmidt, Manfred Schimmler, Heiko Schröder: A Morphological Approach to Hough Transform on an Instruction Systolic Array. Computers and Artificial Intelligence 18(6) (1999)

Bertil Schmidt, Manfred Schimmler: A Parallel Accelerator Architecture for Multimedia Video Compression. Euro-Par 1999: 950-960

Bertil Schmidt, Manfred Schimmler, Heiko Schröder: Long Operand Arithmetic on Instruction Systolic Computer Architectures and Its Application in RSA Cryptography. Euro-Par 1998: 916-922

Bertil Schmidt, Manfred Schimmler, Heiko Schröder: Morphological Hough Transform on the Instruction Systolic Array. Euro-Par 1997: 798-806

Manfred Schimmler, Hans-Werner Lang, Rüdiger Maaß: The Instruction Systolic Array - Implementation of a Low-Cost Parallel Architecture as Add-On Board for Personal Computers. HPCN 1994: 487-488

Manfred Schimmler: Parallel strong orientation on a mesh connected computer. Parallel Computing 17(6-7): 657-664 (1991)

Michael Phieler, Manfred Schimmler, Hartmut Schmeck: A Reconfigurable Instruction Systolic Array. Fault-Tolerant Computing Systems 1991: 312-323

Manfred Schimmler, Hartmut Schmeck: A Fault Tolerant and High Speed Instruction Systolic Array. VLSI 1991: 471-480

E. V. Krishnamurthy, Manfred Kunde, Manfred Schimmler, Heiko Schröder: Systolic algorithm for tensor products of matrices: implementation and applications. Parallel Computing 13(3): 301-308 (1990)

Manfred Schimmler, Heiko Schröder: A simple systolic method to find all bridges of an undirected graph. Parallel Computing 12(1): 107-111 (1989)

Manfred Schimmler, Christoph Starke: A Correction Network for N-Sorters. SIAM J. Comput. 18(6): 1179-1187 (1989)

Manfred Kunde, Hans-Werner Lang, Manfred Schimmler, Hartmut Schmeck, Heiko Schröder: The instruction systolic array and its relation to other models of parallel computers. Parallel Computing 7(1): 25-39 (1988)

Manfred Schimmler, Christoph Starke: A Correction Network for N-Sorters. AWOC 1988: 444-455

Manfred Schimmler, Heiko Schröder: A Simple Systolic Method to Find all Bridges of an Undirected Graph. WG 1988: 262-267

Hans-Werner Lang, Manfred Schimmler, Hartmut Schmeck, Heiko Schröder: Systolic Sorting on a Mesh-Connected Network. IEEE Trans. Computers 34(7): 652-658 (1985)

Hans-Werner Lang, Manfred Schimmler, Hartmut Schmeck, Heiko Schröder: A Method for Realistic Comparisons of Sorting Algorithms for VLSI. FODO 1985: 309-316

Hans-Werner Lang, Manfred Schimmler, Hartmut Schmeck, Heiko Schröder: A Fast Sorting Algorithm for VLSI. ICALP 1983: 408-419