Michael S. Schlansker

Michael S. Schlansker: Cydra 5. Encyclopedia of Parallel Computing 2011: 488-497

Michael S. Schlansker, Nagabhushan Chitlur, Erwin Oertli, Paul M. Stillwell Jr., Linda Rankin, Dennis Bradford, Richard J. Carter, Jayaram Mudigonda, Nathan L. Binkert, Norman P. Jouppi: High-performance ethernet-based communications for future multi-core processors. SC 2007: 37

Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker, Brad Calder: Exploiting Fine-Grained Data Parallelism with Chip Multiprocessors and Fast Barriers. MICRO 2006: 235-246

Jack Sampson, Rubén González, Jean-Francois Collard, Norman P. Jouppi, Michael S. Schlansker: Fast synchronization for chip multiprocessors. SIGARCH Computer Architecture News 33(4): 64-69 (2005)

Hongtao Zhong, Kevin Fan, Scott A. Mahlke, Michael S. Schlansker: A Distributed Control Path Architecture for VLIW Processors. IEEE PACT 2005: 197-206

Michael S. Schlansker: In Memory of Bob Rau. MICRO 2003: 165-168

B. Ramakrishna Rau, Michael S. Schlansker: Embedded Computer Architecture and Automation. IEEE Computer 34(4): 75-83 (2001)

Michael S. Schlansker, Chris J. Newburn: Guest Editors' Introduction. J. Instruction-Level Parallelism 3 (2001)

Scott A. Mahlke, Rajiv A. Ravindran, Michael S. Schlansker, Robert Schreiber, Timothy Sherwood: Bitwidth cognizant architecture synthesis of custom hardwareaccelerators. IEEE Trans. on CAD of Integrated Circuits and Systems 20(11): 1355-1371 (2001)

Shail Aditya, Michael S. Schlansker: ShiftQ: a bufferred interconnect for custom loop accelerators. CASES 2001: 158-167

Michael S. Schlansker, B. Ramakrishna Rau: EPIC: Explicititly Parallel Instruction Computing. IEEE Computer 33(2): 37-45 (2000)

B. Ramakrishna Rau, Michael S. Schlansker: Embedded Computing: New Directions in Architecture and Automation. HiPC 2000: 225-244

Michael S. Schlansker, Scott A. Mahlke, Richard Johnson: Control CPR: A Branch Height Reduction Optimization for EPIC Architectures. PLDI 1999: 155-168

Thomas M. Conte, Pradeep K. Dubey, Matthew D. Jennings, Ruby B. Lee, Alex Peleg, Salliah Rathnam, Michael S. Schlansker, Peter Song, Andrew Wolfe: Challenges to Combining General-Purpose and Multimedia Processors. IEEE Computer 30(12): 33-37 (1997)

Michael S. Schlansker, Thomas M. Conte, James C. Dehnert, Kemal Ebcioglu, Jesse Zhixi Fang, Carol L. Thompson: Compilers for Instruction-Level Parallelism. IEEE Computer 30(12): 63-69 (1997)

Michael S. Schlansker, Vinod Kathail: Techniques for critical path reduction of scalar programs. International Journal of Parallel Programming 25(3): 147-181 (1997)

Michael S. Schlansker, Vinod Kathail, Sadun Anik: Parallelization of Control Recurrences for ILP Processors. International Journal of Parallel Programming 24(1): 65-102 (1996)

Chandra Chekuri, Richard Johnson, Rajeev Motwani, B. Natarajan, B. Ramakrishna Rau, Michael S. Schlansker: Profile-driven Instruction Level Parallel Scheduling with Application to Super Blocks. MICRO 1996: 58-67

Richard Johnson, Michael S. Schlansker: Analysis Techniques for Predicated Code. MICRO 1996: 100-113

David M. Gillies, Roy Dz-Ching Ju, Richard Johnson, Michael S. Schlansker: Global Predicate Analysis and Its Application to Register Allocation. MICRO 1996: 114-125

Michael S. Schlansker, Vinod Kathail: Critical path reduction for scalar programs. MICRO 1995: 57-69

B. Natarajan, Michael S. Schlansker: Spill-free parallel scheduling of basic blocks. MICRO 1995: 119-124

Michael S. Schlansker, Vinod Kathail, Sadun Anik: Height reduction of control recurrences for ILP processors. MICRO 1994: 40-51

Scott A. Mahlke, William Y. Chen, Roger A. Bringmann, Richard E. Hank, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker: Sentinel Scheduling for VLIW and Superscalar Processors. ACM Trans. Comput. Syst. 11(4): 376-408 (1993)

Michael S. Schlansker, Vinod Kathail: Acceleration of First and Higher Order Recurrences on Processors with Instruction Level Parallelism. LCPC 1993: 406-429

Scott A. Mahlke, William Y. Chen, Wen-mei W. Hwu, B. Ramakrishna Rau, Michael S. Schlansker: Sentinel Scheduling for VLIW and Superscalar Processors. ASPLOS 1992: 238-247

B. Ramakrishna Rau, Michael S. Schlansker, Parthasarathy P. Tirumalai: Code generation schema for modulo scheduled loops. MICRO 1992: 158-169

B. Ramakrishna Rau, Meng Lee, Parthasarathy P. Tirumalai, Michael S. Schlansker: Register Allocation for Software Pipelined Loops. PLDI 1992: 283-299

Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker: Parallelization of WHILE loops on pipelined architectures. The Journal of Supercomputing 5(2-3): 119-136 (1991)

Parthasarathy P. Tirumalai, Meng Lee, Michael S. Schlansker: Parallelization of loops with exits on pipelined architectures. SC 1990: 200-212

B. Ramakrishna Rau, Michael S. Schlansker, David W. L. Yen: The Cydram 5 Stride-Insensitive Memory System. ICPP (1) 1989: 242-246

Pradip Bose, B. Ramakrishna Rau, Michael S. Schlansker: Systematically derived instruction sets for high-level language support. ACM Southeast Regional Conference 1982: 73-84