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Carl Sechen
2010 – today
- 2012
[c49]- 2011
- [c48]Mohammad Rahman, Ryan Afonso, Hiran Tennakoon, Carl Sechen: Power reduction via separate synthesis and physical libraries. DAC 2011: 627-632
- [c47]Mohammad Rahman, Hiran Tennakoon, Carl Sechen: Power reduction via near-optimal library-based cell-size selection. DATE 2011: 867-870
- [c46]Chiu-wei Pan, Zhao Wang, Yuanchen Song, Carl Sechen: Power efficient partial product compression. ACM Great Lakes Symposium on VLSI 2011: 347-350
2000 – 2009
- 2008
- [j13]Hiran Tennakoon, Carl Sechen: Nonconvex Gate Delay Modeling and Delay Optimization. IEEE Trans. on CAD of Integrated Circuits and Systems 27(9): 1583-1594 (2008)
- 2007
- [c45]
- 2006
- [c44]Jinyao Zhang, Miodrag Vujkovic, David Wadkins, Carl Sechen: Post-layout energy-delay analysis of parallel multipliers. ISCAS 2006
- 2005
- [c43]Hiran Tennakoon, Carl Sechen: Efficient and accurate gate sizing with piecewise convex delay models. DAC 2005: 807-812
- [c42]Xinyu Guo, Carl Sechen: High Speed Redundant Adder and Divider in Output Prediction Logic. ISVLSI 2005: 34-41
- [c41]Sheng Sun, Yi Han, Xinyu Guo, Kian Haur Chong, Larry McMurchie, Carl Sechen: 409ps 4.7 FO4 64b Adder Based on Output Prediction Logic in 0.18um CMOS. ISVLSI 2005: 52-58
- [c40]Miodrag Vujkovic, David Wadkins, Carl Sechen: Efficient Post-layout Power-Delay Curve Generation. PATMOS 2005: 393-403
- 2004
- [c39]Miodrag Vujkovic, David Wadkins, William Swartz, Carl Sechen: Efficient timing closure without timing driven placement and routing. DAC 2004: 268-273
- 2003
- [j12]Jovanka Ciric, Carl Sechen: Efficient canonical form for Boolean matching of complex functions in large libraries. IEEE Trans. on CAD of Integrated Circuits and Systems 22(5): 535-544 (2003)
- [c38]Carl Sechen, Barbara Chappel, Jim Hogan, Andrew Moore, Tadahiko Nakamura, Gregory A. Northrop, Anjaneya Thakar: Libraries: lifejacket or straitjacket. DAC 2003: 642-643
- [c37]Su Kio, Kian Haur Chong, Carl Sechen: A low power delayed-clocks generation and distribution system. ISCAS (5) 2003: 445-448
- 2002
- [j11]G. N. Hoyer, Gin Yee, Carl Sechen: Locally clocked pipelines and dynamic logic. IEEE Trans. VLSI Syst. 10(1): 58-62 (2002)
- [c36]Miodrag Vujkovic, Carl Sechen: Optimized power-delay curve generation for standard cell ICs. ICCAD 2002: 387-394
- [c35]Hiran Tennakoon, Carl Sechen: Gate sizing using Lagrangian relaxation combined with a fast gradient-based pre-processing step. ICCAD 2002: 395-402
- [c34]Larry McMurchie, Carl Sechen: WTA: waveform-based timing analysis for deep submicron circuits. ICCAD 2002: 625-631
- [c33]Miodrag Vujkovic, Carl Sechen: Optimized Power-Delay Curve Generation for Standard Cell ICs. IWLS 2002: 413-418
- 2001
- [j10]Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen: Timing- and crosstalk-driven area routing. IEEE Trans. on CAD of Integrated Circuits and Systems 20(4): 528-544 (2001)
- [c32]Sheng Sun, Larry McMurchie, Carl Sechen: A High-Performance 64-bit Adder Implemented in Output Prediction Logic. ARVLSI 2001: 213-223
- [c31]Rob A. Rutenbar, Max Baron, Thomas Daniel, Rajeev Jayaraman, Zvi Or-Bach, Jonathan Rose, Carl Sechen: Panel: (When) Will FPGAs Kill ASICs? DAC 2001: 321-322
- [c30]
- [c29]Jovanka Ciric, Carl Sechen: Efficient Canonical Form for Boolean Matching of Complex Functions in Large Libraries. ICCAD 2001: 610-617
- 2000
- [j9]Gin Yee, Carl Sechen: Clock-delayed domino for dynamic circuit design. IEEE Trans. VLSI Syst. 8(4): 425-430 (2000)
- [c28]Jovanka Ciric, Gin Yee, Carl Sechen: Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. DATE 2000: 277-282
- [c27]Larry McMurchie, Su Kio, Gin Yee, Tyler Thorp, Carl Sechen: Output Prediction Logic: A High-Performance CMOS Design Technique. ICCD 2000: 247-
- [c26]Gin Yee, Tyler Thorp, Ron Christopherson, Ban P. Wang, Carl Sechen: An Automated Shielding Algorithm and Tool For Dynamic Circuits. ISQED 2000: 369-374
1990 – 1999
- 1999
- [j8]Le-Chin Eugene Liu, Carl Sechen: Multilayer chip-level global routing using an efficient graph-based Steiner tree heuristic. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1442-1451 (1999)
- [j7]Le-Chin Eugene Liu, Carl Sechen: Multilayer pin assignment for macro cell circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1452-1461 (1999)
- [j6]Hsiao-Ping Tseng, Carl Sechen: A gridless multilayer router for standard cell circuits using CTMcells. IEEE Trans. on CAD of Integrated Circuits and Systems 18(10): 1462-1479 (1999)
- [c25]Tatjana Serdar, Carl Sechen: AKORD: transistor level and mixed transistor/gate level placement tool for digital data paths. ICCAD 1999: 91-97
- [c24]
- 1998
- [c23]Hsiao-Ping Tseng, Louis Scheffer, Carl Sechen: Timing and Crosstalk Driven Area Routing. DAC 1998: 378-381
- [c22]Tyler Thorp, Gin Yee, Carl Sechen: Domino logic synthesis using complex static gates. ICCAD 1998: 242-247
- [c21]
- 1997
- [j5]Qicheng Yu, Carl Sechen: Efficient approximation of symbolic network functions using matroid intersection algorithms. IEEE Trans. on CAD of Integrated Circuits and Systems 16(10): 1073-1081 (1997)
- [j4]Wern-Jieh Sun, Carl Sechen: A parallel standard cell placement algorithm. IEEE Trans. on CAD of Integrated Circuits and Systems 16(11): 1342-1357 (1997)
- [c20]Martin Lefebvre, David Marple, Carl Sechen: The Future of Custom Cell Generation in Physical Synthesis. DAC 1997: 446-451
- [c19]Le-Chin Eugene Liu, Carl Sechen: Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic. ED&TC 1997: 311-318
- [c18]Hsiao-Ping Tseng, Carl Sechen: A gridless multi-layer router for standard cell circuits using CTM cells. ED&TC 1997: 319-326
- 1996
- [c17]
- [c16]Bingzhong Guan, Carl Sechen: Large Standard Cell Libraries and Their Impact on Layout Area and Circuit Performanc. ICCD 1996: 378-383
- 1995
- [j3]Wern-Jieh Sun, Carl Sechen: Efficient and effective placement for very large circuits. IEEE Trans. on CAD of Integrated Circuits and Systems 14(3): 349-359 (1995)
- [j2]Ted Stanion, Debashis Bhattacharya, Carl Sechen: An efficient method for generating exhaustive test sets. IEEE Trans. on CAD of Integrated Circuits and Systems 14(12): 1516-1525 (1995)
- [c15]Ted Stanion, Carl Sechen: Quasi-algebraic decompositions of switching functions. ARVLSI 1995: 358-367
- [c14]Ted Stanion, Carl Sechen: A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis. DAC 1995: 60-64
- [c13]William Swartz, Carl Sechen: Timing Driven Placement for Large Standard Cell Circuits. DAC 1995: 211-215
- [c12]Kalapi Roy-Neogi, Carl Sechen: Multiple FPGA Partitioning with Performance Optimization. FPGA 1995: 146-152
- [c11]Jer-Jaw Hsu, Carl Sechen: Accurate Extraction of Simplified Symbolic Pole/Zero Expressions for Large Analog IC's. ISCAS 1995: 2083-2087
- [c10]Qicheng Yu, Carl Sechen: Efficient Approximation of Symbolic Network Function Using Matroid Intersection Algorithms. ISCAS 1995: 2088-2091
- 1994
- [j1]Ted Stanion, Carl Sechen: Boolean division and factorization using binary decision diagrams. IEEE Trans. on CAD of Integrated Circuits and Systems 13(9): 1179-1184 (1994)
- [c9]Wern-Jieh Sun, Carl Sechen: A loosely coupled parallel algorithm for standard cell placement. ICCAD 1994: 137-144
- [c8]Qicheng Yu, Carl Sechen: Approximate symbolic analysis of large analog integrated circuits. ICCAD 1994: 664-671
- [c7]Kalapi Roy-Neogi, Bingzhong Guan, Carl Sechen: A Sea-of-Gates Style FPGA Placement Algorithm. VLSI Design 1994: 221-224
- 1993
- [c6]Wern-Jieh Sun, Carl Sechen: Efficient and effective placement for very large circuits. ICCAD 1993: 170-177
- [c5]
- [c4]Ted Stanion, Carl Sechen: Maximum projections of don't care conditions in a Boolean network. ICCAD 1993: 674-679
- 1990
- [c3]William Swartz, Carl Sechen: New Algorithms for the Placement and Routing of Macro Cells. ICCAD 1990: 336-339
1980 – 1989
- 1988
- [c2]Carl Sechen: Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing. DAC 1988: 73-80
- 1986
- [c1]Carl Sechen, Alberto L. Sangiovanni-Vincentelli: TimberWolf3.2: a new standard cell placement and global routing package. DAC 1986: 432-439
Coauthor Index
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last updated on 2012-12-02 21:27 CET by the dblp team