Please note: This is a beta version of the new dblp website.
You can find the classic dblp view of this page here.
You can find the classic dblp view of this page here.
Carl-Johan H. Seger
2000 – 2009
- 2007
[c29]Sara Adams, Magnus Björk, Thomas F. Melham, Carl-Johan H. Seger: Automatic Abstraction in Symbolic Trajectory Evaluation. FMCAD 2007: 127-135- 2005
- [j13]Carl-Johan H. Seger, Robert B. Jones, John W. O'Leary, Thomas F. Melham, Mark Aagaard, Clark Barrett, Don Syme: An industrially effective environment for formal hardware verification. IEEE Trans. on CAD of Integrated Circuits and Systems 24(9): 1381-1405 (2005)
- 2004
- [c28]
- 2003
- [j12]Jin Yang, Carl-Johan H. Seger: Introduction to generalized symbolic trajectory evaluation. IEEE Trans. VLSI Syst. 11(3): 345-353 (2003)
- 2002
- [c27]Jin Yang, Carl-Johan H. Seger: Generalized Symbolic Trajectory Evaluation - Abstraction in Action. FMCAD 2002: 70-87
- 2001
- [j11]Robert B. Jones, John W. O'Leary, Carl-Johan H. Seger, Mark Aagaard, Thomas F. Melham: Practical Formal Verification in Microprocessor Design. IEEE Design & Test of Computers 18(4): 16-25 (2001)
- [c26]John Moondanos, Carl-Johan H. Seger, Ziyad Hanna, Daher Kaiss: CLEVER: Divide and Conquer Combinational Logic Equivalence VERification with False Negative Elimination. CAV 2001: 131-143
- [c25]
- 2000
- [c24]Carl-Johan H. Seger: Connecting Bits with Floating-Point Numbers: Model Checking and Theorem Proving in Practice. CADE 2000: 235
- [c23]Mark Aagaard, Robert B. Jones, Roope Kaivola, Katherine R. Kohatsu, Carl-Johan H. Seger: Formal verification of iterative algorithms in microprocessors. DAC 2000: 201-206
- [c22]Mark Aagaard, Robert B. Jones, Thomas F. Melham, John W. O'Leary, Carl-Johan H. Seger: A Methodology for Large-Scale Hardware Verification. FMCAD 2000: 263-282
- [c21]Carl-Johan H. Seger: Combining functional programming and hardware verification (abstract of invited talk). ICFP 2000: 244
1990 – 1999
- 1999
- [j10]Scott Hazelhurst, Carl-Johan H. Seger: Model Checking Lattices: Using and reasoning about information orders for abstraction. Logic Journal of the IGPL 7(3): 375-411 (1999)
- [c20]Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger: Parametric Representations of Boolean Constraints. DAC 1999: 402-407
- [c19]Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger: Lifted-FL: A Pragmatic Implementation of Combined Model Checking and Theorem Proving. TPHOLs 1999: 323-340
- 1998
- [c18]Mark Aagaard, Robert B. Jones, Carl-Johan H. Seger: Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment. DAC 1998: 538-541
- [c17]Carl-Johan H. Seger: Formal Methods in CAD from an Industrial Perspective (abstract). FMCAD 1998: 203
- [c16]
- 1997
- [c15]Scott Hazelhurst, Carl-Johan H. Seger: Symbolic Trajectory Evaluation. Formal Hardware Verification 1997: 3-78
- 1996
- [c14]
- 1995
- [b1]Janusz A. Brzozowski, Carl-Johan H. Seger: Asynchronous circuits. Monographs in computer science, Springer 1995, ISBN 978-0-387-94420-3, pp. I-XVI, 1-404
- [j9]Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger: Automatic Verification of Asynchronous Circuits. IEEE Design & Test of Computers 12(1): 24-31 (1995)
- [j8]Carl-Johan H. Seger, Randal E. Bryant: Formal Verification by Symbolic Evaluation of Partially-Ordered Trajectories. Formal Methods in System Design 6(2): 147-189 (1995)
- [j7]Scott Hazelhurst, Carl-Johan H. Seger: A simple theorem prover based on symbolic trajectory evaluation and BDD's. IEEE Trans. on CAD of Integrated Circuits and Systems 14(4): 413-422 (1995)
- [c13]Mark Aagaard, Carl-Johan H. Seger: The formal verification of a pipelined double-precision IEEE floating-point multiplier. ICCAD 1995: 7-10
- 1994
- [j6]Carl-Johan H. Seger, Janusz A. Brzozowski: Generalized Ternary Simulation of Sequential Circuits. ITA 28(3-4): 159-186 (1994)
- [c12]Scott Hazelhurst, Carl-Johan H. Seger: Composing Symbolic Trajectory Evaluation Results. CAV 1994: 273-285
- [c11]
- [c10]Trevor Wing Sang Lee, Mark R. Greenstreet, Carl-Johan H. Seger: Automatic Verification of Refinement. ICCD 1994: 225-229
- [c9]Carl-Johan H. Seger, Randal E. Bryant: Digital Circuit Verification Using Partially-Ordered State Models. ISMVL 1994: 2-7
- [e1]Jeffrey J. Joyce, Carl-Johan H. Seger (Eds.): Higher Order Logic Theorem Proving and its Applications, 6th International Workshop, HUG '93, Vancouver, BC, Canada, August 11-13, 1993, Proceedings. Lecture Notes in Computer Science 780, Springer 1994, ISBN 3-540-57826-9
- 1993
- [c8]Jeffrey J. Joyce, Carl-Johan H. Seger: Linking BDD-Based Symbolic Evaluation to Interactive Theorem-Proving. DAC 1993: 469-474
- [c7]Jeffrey J. Joyce, Carl-Johan H. Seger: The HOL-Voss System: Model-Checking inside a General-Purpose Theorem-Prover. HUG 1993: 185-198
- [c6]Zheng Zhu, Jeffrey J. Joyce, Carl-Johan H. Seger: Verification of the Tamarack-3 Microprocessor in a Hybrid Verification Environment. HUG 1993: 253-266
- [c5]Sreeranga P. Rajan, Jeffrey J. Joyce, Carl-Johan H. Seger: From Abstract Data Types to Shift Registers: A Case Study in Formal Specification and Verification at Differing Levels of Abstraction using Theorem Proving and Symbolic Simulation. HUG 1993: 489-500
- 1991
- [j5]Carl-Johan H. Seger: On the Existence of Speed-Independent Circuits. Theor. Comput. Sci. 86(2): 343-364 (1991)
- [c4]Carl-Johan H. Seger, Jeffrey J. Joyce: A Two-Level Formal Verification Methodology using HOL and COSMOS. CAV 1991: 299-309
- [c3]Randal E. Bryant, Derek L. Beatty, Carl-Johan H. Seger: Formal Hardware Verification by Symbolic Ternary Trajectory Evaluation. DAC 1991: 397-402
- 1990
- [c2]Randal E. Bryant, Carl-Johan H. Seger: Formal Verification of Digital Circuits Using Symbolic Ternary System Models. CAV 1990: 33-43
1980 – 1989
- 1989
- [j4]Janusz A. Brzozowski, Carl-Johan H. Seger: A unified framework for race analysis of asynchronous networks. J. ACM 36(1): 20-45 (1989)
- 1988
- [j3]Carl-Johan H. Seger, Janusz A. Brzozowski: An Optimistic Ternary Simulation of Gate Races. Theor. Comput. Sci. 61: 49-66 (1988)
- 1987
- [j2]Janusz A. Brzozowski, Carl-Johan H. Seger: A Characterization of Ternary Simulation of Gate Networks. IEEE Trans. Computers 36(11): 1318-1327 (1987)
- 1986
- [j1]David J. Taylor, Carl-Johan H. Seger: Robust Storage Structures for Crash Recovery. IEEE Trans. Computers 35(4): 288-295 (1986)
- [c1]Janusz A. Brzozowski, Carl-Johan H. Seger: Correspondence between Ternary Simulation and Binary Race Analysis in Gate Networks (Extended Summary). ICALP 1986: 69-78
Coauthor Index
data released under the ODC-BY 1.0 license. See also our legal information page
last updated on 2012-12-02 21:51 CET by the dblp team