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Rimantas Seinauskas
2010 – today
- 2012
[j7]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: Evaluation of testability enhancement using software prototype. IET Computers & Digital Techniques 6(3): 166-172 (2012)- 2011
- [j6]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: Functional fault models for non-scan sequential circuits. Microelectronics Reliability 51(12): 2402-2411 (2011)
2000 – 2009
- 2009
- [j5]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: Functional delay test generation based on software prototype. Microelectronics Reliability 49(12): 1578-1585 (2009)
- 2008
- [j4]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: Test generation at the algorithm-level for gate-level fault coverage. Microelectronics Reliability 48(7): 1093-1101 (2008)
- [c5]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: Development of Functional Delay Tests. DSD 2008: 626-632
- 2007
- [j3]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: Functional Test Generation Based on Combined Random and Deterministic Search Methods. Informatica, Lith. Acad. Sci. 18(1): 3-26 (2007)
- [c4]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: Transition Faults Testing Based on Functional Delay Tests. DDECS 2007: 371-376
- [c3]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: The Criteria of Functional Delay Test Quality Assessment. DSD 2007: 207-214
- 2006
- [c2]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: Transition Fault Test Reuse. DSD 2006: 323-330
- 2005
- [j2]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: The Realization-Independent Testing Based on the Black Box Fault Models. Informatica, Lith. Acad. Sci. 16(1): 19-36 (2005)
- [c1]Eduardas Bareisa, Vacius Jusas, Kestutis Motiejunas, Rimantas Seinauskas: Functional Test Generation Remote Tool. DSD 2005: 192-195
- 2003
- [j1]Eduardas Bareisa, Kestutis Motiejunas, Rimantas Seinauskas: Identifying Legal and Illegal States in Synchronous Sequential Circuits Using Test Generation. Informatica, Lith. Acad. Sci. 14(2): 135-154 (2003)
Coauthor Index
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last updated on 2012-12-02 20:56 CET by the dblp team