DBLP: Sharad C. Seth

	2012
c41		Dongyuan Zhan, Hong Jiang, Sharad C. Seth: Locality & utility co-optimization for practical capacity management of shared last level caches. ICS 2012: 279-290
	2011
c40		Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya: Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects. Asian Test Symposium 2011: 297-302
c39		George Nagy, Sharad C. Seth, Dongpu Jin, David W. Embley, Spencer Machado, Mukkai S. Krishnamoorthy: Data Extraction from Web Tables: The Devil is in the Details. ICDAR 2011: 242-246
c38		David W. Embley, Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth: Factoring Web Tables. IEA/AIE (1) 2011: 253-263
	2010
j25		Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya: PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture. J. Low Power Electronics 6(3): 457-468 (2010)
c37		Sharad C. Seth, Ramana Chakradhar Jandhyala, Mukkai S. Krishnamoorthy, George Nagy: Analysis and taxonomy of column header categories for web tables. Document Analysis Systems 2010: 81-88
c36		Dongyuan Zhan, Hong Jiang, Sharad C. Seth: Exploiting set-level non-uniformity of capacity demand to enhance CMP cooperative caching. IPDPS 2010: 1-10
c35		Dongyuan Zhan, Hong Jiang, Sharad C. Seth: STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches. MICRO 2010: 163-174
c34		Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya: A Unified Solution to Scan Test Volume, Time, and Power Minimization. VLSI Design 2010: 9-14
c33		Zhen Chen, Sharad C. Seth, Dong Xiang: A novel hybrid delay testing scheme with low test power, volume, and time. VTS 2010: 307-312
	2009
j24		George Nagy, Sharad C. Seth, Mahesh Viswanathan: Comment: Projection Methods Require Black Border Removal. IEEE Trans. Pattern Anal. Mach. Intell. 31(4): 762 (2009)
c32		Raghav Krishna Padmanabhan, Ramana Chakradhar Jandhyala, Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth, William Silversmith: Interactive Conversion of Web Tables. GREC 2009: 25-36
c31		Ramana Chakradhar Jandhyala, Mukkai S. Krishnamoorthy, George Nagy, Raghav K. Padmanabhan, Sharad C. Seth, William Silversmith: From Tessellations to Table Interpretation. Calculemus/MKM 2009: 422-437
	2008
j23		Indranil Saha, Bhargab B. Bhattacharya, Sheng Zhang, Sharad C. Seth: Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid. Fundam. Inform. 89(2-3): 331-344 (2008)
c30		Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram: Efficient Selection of Observation Points for Functional Tests. ISQED 2008: 236-241
r2		Sharad C. Seth, Ashok Samal: Conflation of Features. Encyclopedia of GIS 2008: 129-133
r1		Ashok Samal, Sharad C. Seth: Feature Extraction, Abstract. Encyclopedia of GIS 2008: 314-320
	2007
c29		Jian Kang, Sharad C. Seth, Vijay Gangaram: Efficient RTL Coverage Metric for Functional Test Selection. VTS 2007: 318-324
	2006
c28		Ashutosh Joshi, George Nagy, Daniel P. Lopresti, Sharad C. Seth: A Maximum-Likelihood Approach to Symbolic Indirect Correlation. ICPR (3) 2006: 99-103
	2005
c27		Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya: Efficient Test Compaction for Pseudo-Random Testing. Asian Test Symposium 2005: 337-342
c26		Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya: On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design. VLSI Design 2005: 491-496
	2004
j22		Ashok Samal, Sharad C. Seth, Kevin Cueto: A feature-based approach to conflation of geospatial sources. International Journal of Geographical Information Science 18(5): 459-489 (2004)
c25		George Nagy, Ashutosh Joshi, Mukkai S. Krishnamoorthy, Yu Lin, Daniel P. Lopresti, Shashank K. Mehta, Sharad C. Seth: A nonparametric classifier for unsegmented text. DRR 2004: 102-108
	2003
j21		Hailong Cui, Sharad C. Seth, Shashank K. Mehta: Modeling Fault Coverage of Random Test Patterns. J. Electronic Testing 19(3): 271-284 (2003)
c24		Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang: Double-Tree Scan: A Novel Low-Power Scan-Path Architecture. ITC 2003: 470-479
c23		Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang: Low-Energy BIST Design for Scan-based Logic Circuits. VLSI Design 2003: 546-551
	2002
c22		Hailong Cui, Sharad C. Seth, Shashank K. Mehta: A Novel Method to Improve the Test Efficiency of VLSI Tests. VLSI Design 2002: 499-504
	2001
c21		Don Sylwester, Sharad C. Seth: Adaptive Segmentation of Document Images. ICDAR 2001: 827-831
c20		Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr: Design Verification and Functional Testing of FiniteState Machines. VLSI Design 2001: 189-195
	2000
j20		Luyang Li, George Nagy, Ashok Samal, Sharad C. Seth, Yihong Xu: Integrated text and line-art extraction from a topographic map. IJDAR 2(4): 177-185 (2000)
c19		Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr: Exploiting don't cares to enhance functional tests. ITC 2000: 538-546
	1999
j19		Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth: A synthesis for testability scheme for finite state machines using clock control. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1780-1792 (1999)
c18		Luyang Li, George Nagy, Ashok Samal, Sharad C. Seth, Yihong Xu: Cooperative Text and Line-Art Extraction from a Topographic Map. ICDAR 1999: 467-470
c17		Shashank K. Mehta, Sharad C. Seth: Empirical Computation of Reject Ratio in VLSI Testing. VLSI Design 1999: 506-511
	1998
c16		Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth: Synthesis of Sequential Circuits with Clock Control to Improve Testability. Asian Test Symposium 1998: 472-
c15		Vishwani D. Agrawal, Sharad C. Seth: Mutually Disjoint Signals and Probability Calculation in Digital Circuits. Great Lakes Symposium on VLSI 1998: 307-312
	1997
c14		George Nagy, Ashok Samal, Sharad C. Seth, T. Fisher, E. Guthmann, K. Kalafala, Luyang Li, Prateek Sarkar, S. Sivasubramaniam, Yihong Xu: A Prototype for Adaptive Association of Street Names with Streets on Maps. GREC 1997: 302-313
c13		Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth: Synthesis for Testability by Two-Clock Control. VLSI Design 1997: 279-283
	1996
c12		Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal: Improving Circuit Testability by Clock Control. Great Lakes Symposium on VLSI 1996: 288-293
	1995
j18		N. Ranganathan, Sharad C. Seth: Conference Reports. IEEE Design & Test of Computers 12(2): 5, 81 (1995)
j17		Kent L. Einspahr, Sharad C. Seth: A switch-level test generation system for synchronous and asynchronous circuits. J. Electronic Testing 6(1): 59-73 (1995)
c11		Stephen D. Scott, Ashok Samal, Sharad C. Seth: HGA: A Hardware-Based Genetic Algorithm. FPGA 1995: 53-59
c10		Don Sylwester, Sharad C. Seth: A trainable, single-pass algorithm for column segmentation. ICDAR 1995: 615-618
c9		Yuhong Yu, Ashok Samal, Sharad C. Seth: A system for recognizing a large class of engineering drawings. ICDAR 1995: 791-794
c8		S. Venkatraman, Sharad C. Seth, Prathima Agrawal: Parallel test generation with low communication overhead. VLSI Design 1995: 116-120
	1994
j16		Yuhong Yu, Ashok Samal, Sharad C. Seth: Isolating symbols from connection lines in a class of engineering drawings. Pattern Recognition 27(3): 391-404 (1994)
c7		Sharad C. Seth, Lee Gowen, Matt Payne, Don Sylwester: Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine. VLSI Design 1994: 29-32
	1993
j15		Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth: Generating Tests for Delay Faults in Nonscan Circuits. IEEE Design & Test of Computers 10(1): 20-28 (1993)
j14		Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth, Mahesh Viswanathan: Syntactic Segmentation and Labeling of Digitized Pages from Technical Journals. IEEE Trans. Pattern Anal. Mach. Intell. 15(7): 737-747 (1993)
j13		D. Das, Sharad C. Seth, Vishwani D. Agrawal: Accurate computation of field reject ratio based on fault latency. IEEE Trans. VLSI Syst. 1(4): 537-545 (1993)
	1992
j12		George Nagy, Sharad C. Seth, Mahesh Viswanathan: A Prototype Document Image Analysis System for Technical Journals. IEEE Computer 25(7): 10-22 (1992)
	1991
c6		Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal: Estimating the Quality of Manufactured Digital Sequential Circuits. ITC 1991: 210-217
	1990
j11		Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat: A Statistical Theory of Digital Circuit Testability. IEEE Trans. Computers 39(4): 582-586 (1990)
c5		Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal: An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. ITC 1990: 712-720
c4		Paul Kenyon, Prathima Agrawal, Sharad C. Seth: High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator. MICRO 1990: 97-106
	1989
j10		Lester Lipsky, Sharad C. Seth: Signal Probabilities in AND-OR Trees. IEEE Trans. Computers 38(11): 1558-1563 (1989)
j9		Bhargab B. Bhattacharya, Sharad C. Seth: Design of Parity Testable Combinational Circuits. IEEE Trans. Computers 38(11): 1580-1584 (1989)
c3		Raghu V. Hudli, Sharad C. Seth: Testability Analysis of Synchronous Sequential Circuits Based on Structural Data. ITC 1989: 364-372
	1987
j8		George Nagy, Sharad C. Seth, Kent L. Einspahr: Decoding Substitution Ciphers by Means of Word Matching with Application to OCR. IEEE Trans. Pattern Anal. Mach. Intell. 9(5): 710-715 (1987)
	1985
c2		Sharad C. Seth: Predicting Fault Coverage from Probabilistic Testability. ITC 1985: 803-807
	1984
j7		Ten-Chuan Hsiao, Sharad C. Seth: An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing. IEEE Trans. Computers 33(10): 934-937 (1984)
j6		Sharad C. Seth, Vishwani D. Agrawal: Characterizing the LSI Yield Equation from Wafer Test Data. IEEE Trans. on CAD of Integrated Circuits and Systems 3(2): 123-126 (1984)
	1983
j5		Sharad C. Seth, Lester Lipsky: A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems. IEEE Trans. Computers 32(8): 754-760 (1983)
	1981
j4		Sharad C. Seth, K. Narayanaswamy: A Graph Model for Pattern-Sensitive Faults in Random Access Memories. IEEE Trans. Computers 30(12): 973-977 (1981)
c1		Vishwani D. Agrawal, Sharad C. Seth, Prathima Agrawal: LSI product quality and fault coverage. DAC 1981: 196-203
	1978
j3		Kolar L. Kodandapani, Sharad C. Seth: On Combinational Networks with Restricted Fan-Out. IEEE Trans. Computers 27(4): 309-318 (1978)
	1977
j2		James M. Steckelberg, Sharad C. Seth: On a Relation Between Algebraic Programs and Turing Machines. Inf. Process. Lett. 6(6): 180-183 (1977)
j1		Sharad C. Seth, Kolar L. Kodandapani: Diagnosis of Faults in Linear Tree Networks. IEEE Trans. Computers 26(1): 29-33 (1977)

2012

c41

Dongyuan Zhan, Hong Jiang, Sharad C. Seth: Locality & utility co-optimization for practical capacity management of shared last level caches. ICS 2012: 279-290

2011

c40

Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya: Diagnosis of Multiple Scan-Chain Faults in the Presence of System Logic Defects. Asian Test Symposium 2011: 297-302

c39

George Nagy, Sharad C. Seth, Dongpu Jin, David W. Embley, Spencer Machado, Mukkai S. Krishnamoorthy: Data Extraction from Web Tables: The Devil is in the Details. ICDAR 2011: 242-246

c38

David W. Embley, Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth: Factoring Web Tables. IEA/AIE (1) 2011: 253-263

2010

j25

Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya: PVT: Unified Reduction of Test Power, Volume, and Test Time Using Double-Tree Scan Architecture. J. Low Power Electronics 6(3): 457-468 (2010)

c37

Sharad C. Seth, Ramana Chakradhar Jandhyala, Mukkai S. Krishnamoorthy, George Nagy: Analysis and taxonomy of column header categories for web tables. Document Analysis Systems 2010: 81-88

c36

Dongyuan Zhan, Hong Jiang, Sharad C. Seth: Exploiting set-level non-uniformity of capacity demand to enhance CMP cooperative caching. IPDPS 2010: 1-10

c35

Dongyuan Zhan, Hong Jiang, Sharad C. Seth: STEM: Spatiotemporal Management of Capacity for Intra-core Last Level Caches. MICRO 2010: 163-174

c34

Zhen Chen, Sharad C. Seth, Dong Xiang, Bhargab B. Bhattacharya: A Unified Solution to Scan Test Volume, Time, and Power Minimization. VLSI Design 2010: 9-14

c33

Zhen Chen, Sharad C. Seth, Dong Xiang: A novel hybrid delay testing scheme with low test power, volume, and time. VTS 2010: 307-312

2009

j24

George Nagy, Sharad C. Seth, Mahesh Viswanathan: Comment: Projection Methods Require Black Border Removal. IEEE Trans. Pattern Anal. Mach. Intell. 31(4): 762 (2009)

c32

Raghav Krishna Padmanabhan, Ramana Chakradhar Jandhyala, Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth, William Silversmith: Interactive Conversion of Web Tables. GREC 2009: 25-36

c31

Ramana Chakradhar Jandhyala, Mukkai S. Krishnamoorthy, George Nagy, Raghav K. Padmanabhan, Sharad C. Seth, William Silversmith: From Tessellations to Table Interpretation. Calculemus/MKM 2009: 422-437

2008

j23

Indranil Saha, Bhargab B. Bhattacharya, Sheng Zhang, Sharad C. Seth: Planar Straight-Line Embedding of Double-Tree Scan Architecture on a Rectangular Grid. Fundam. Inform. 89(2-3): 331-344 (2008)

c30

Jian Kang, Sharad C. Seth, Yi-Shing Chang, Vijay Gangaram: Efficient Selection of Observation Points for Functional Tests. ISQED 2008: 236-241

Sharad C. Seth, Ashok Samal: Conflation of Features. Encyclopedia of GIS 2008: 129-133

Ashok Samal, Sharad C. Seth: Feature Extraction, Abstract. Encyclopedia of GIS 2008: 314-320

2007

c29

Jian Kang, Sharad C. Seth, Vijay Gangaram: Efficient RTL Coverage Metric for Functional Test Selection. VTS 2007: 318-324

2006

c28

Ashutosh Joshi, George Nagy, Daniel P. Lopresti, Sharad C. Seth: A Maximum-Likelihood Approach to Symbolic Indirect Correlation. ICPR (3) 2006: 99-103

2005

c27

Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya: Efficient Test Compaction for Pseudo-Random Testing. Asian Test Symposium 2005: 337-342

c26

Sheng Zhang, Sharad C. Seth, Bhargab B. Bhattacharya: On Finding Consecutive Test Vectors in a Random Sequence for Energy-Aware BIST Design. VLSI Design 2005: 491-496

2004

j22

Ashok Samal, Sharad C. Seth, Kevin Cueto: A feature-based approach to conflation of geospatial sources. International Journal of Geographical Information Science 18(5): 459-489 (2004)

c25

George Nagy, Ashutosh Joshi, Mukkai S. Krishnamoorthy, Yu Lin, Daniel P. Lopresti, Shashank K. Mehta, Sharad C. Seth: A nonparametric classifier for unsegmented text. DRR 2004: 102-108

2003

j21

Hailong Cui, Sharad C. Seth, Shashank K. Mehta: Modeling Fault Coverage of Random Test Patterns. J. Electronic Testing 19(3): 271-284 (2003)

c24

Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang: Double-Tree Scan: A Novel Low-Power Scan-Path Architecture. ITC 2003: 470-479

c23

Bhargab B. Bhattacharya, Sharad C. Seth, Sheng Zhang: Low-Energy BIST Design for Scan-based Logic Circuits. VLSI Design 2003: 546-551

2002

c22

Hailong Cui, Sharad C. Seth, Shashank K. Mehta: A Novel Method to Improve the Test Efficiency of VLSI Tests. VLSI Design 2002: 499-504

2001

c21

Don Sylwester, Sharad C. Seth: Adaptive Segmentation of Document Images. ICDAR 2001: 827-831

c20

Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr: Design Verification and Functional Testing of FiniteState Machines. VLSI Design 2001: 189-195

2000

j20

Luyang Li, George Nagy, Ashok Samal, Sharad C. Seth, Yihong Xu: Integrated text and line-art extraction from a topographic map. IJDAR 2(4): 177-185 (2000)

c19

Mark W. Weiss, Sharad C. Seth, Shashank K. Mehta, Kent L. Einspahr: Exploiting don't cares to enhance functional tests. ITC 2000: 538-546

1999

j19

Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth: A synthesis for testability scheme for finite state machines using clock control. IEEE Trans. on CAD of Integrated Circuits and Systems 18(12): 1780-1792 (1999)

c18

Luyang Li, George Nagy, Ashok Samal, Sharad C. Seth, Yihong Xu: Cooperative Text and Line-Art Extraction from a Topographic Map. ICDAR 1999: 467-470

c17

Shashank K. Mehta, Sharad C. Seth: Empirical Computation of Reject Ratio in VLSI Testing. VLSI Design 1999: 506-511

1998

c16

Kent L. Einspahr, Shashank K. Mehta, Sharad C. Seth: Synthesis of Sequential Circuits with Clock Control to Improve Testability. Asian Test Symposium 1998: 472-

c15

Vishwani D. Agrawal, Sharad C. Seth: Mutually Disjoint Signals and Probability Calculation in Digital Circuits. Great Lakes Symposium on VLSI 1998: 307-312

1997

c14

George Nagy, Ashok Samal, Sharad C. Seth, T. Fisher, E. Guthmann, K. Kalafala, Luyang Li, Prateek Sarkar, S. Sivasubramaniam, Yihong Xu: A Prototype for Adaptive Association of Street Names with Streets on Maps. GREC 1997: 302-313

c13

Shashank K. Mehta, Kent L. Einspahr, Sharad C. Seth: Synthesis for Testability by Two-Clock Control. VLSI Design 1997: 279-283

1996

c12

Kent L. Einspahr, Sharad C. Seth, Vishwani D. Agrawal: Improving Circuit Testability by Clock Control. Great Lakes Symposium on VLSI 1996: 288-293

1995

j18

N. Ranganathan, Sharad C. Seth: Conference Reports. IEEE Design & Test of Computers 12(2): 5, 81 (1995)

j17

Kent L. Einspahr, Sharad C. Seth: A switch-level test generation system for synchronous and asynchronous circuits. J. Electronic Testing 6(1): 59-73 (1995)

c11

Stephen D. Scott, Ashok Samal, Sharad C. Seth: HGA: A Hardware-Based Genetic Algorithm. FPGA 1995: 53-59

c10

Don Sylwester, Sharad C. Seth: A trainable, single-pass algorithm for column segmentation. ICDAR 1995: 615-618

Yuhong Yu, Ashok Samal, Sharad C. Seth: A system for recognizing a large class of engineering drawings. ICDAR 1995: 791-794

S. Venkatraman, Sharad C. Seth, Prathima Agrawal: Parallel test generation with low communication overhead. VLSI Design 1995: 116-120

1994

j16

Yuhong Yu, Ashok Samal, Sharad C. Seth: Isolating symbols from connection lines in a class of engineering drawings. Pattern Recognition 27(3): 391-404 (1994)

Sharad C. Seth, Lee Gowen, Matt Payne, Don Sylwester: Logic Simulation Using an Asynchronous Parallel Discrete-Event Simulation Model on a SIMD Machine. VLSI Design 1994: 29-32

1993

j15

Prathima Agrawal, Vishwani D. Agrawal, Sharad C. Seth: Generating Tests for Delay Faults in Nonscan Circuits. IEEE Design & Test of Computers 10(1): 20-28 (1993)

j14

Mukkai S. Krishnamoorthy, George Nagy, Sharad C. Seth, Mahesh Viswanathan: Syntactic Segmentation and Labeling of Digitized Pages from Technical Journals. IEEE Trans. Pattern Anal. Mach. Intell. 15(7): 737-747 (1993)

j13

D. Das, Sharad C. Seth, Vishwani D. Agrawal: Accurate computation of field reject ratio based on fault latency. IEEE Trans. VLSI Syst. 1(4): 537-545 (1993)

1992

j12

George Nagy, Sharad C. Seth, Mahesh Viswanathan: A Prototype Document Image Analysis System for Technical Journals. IEEE Computer 25(7): 10-22 (1992)

1991

Dharam Vir Das, Sharad C. Seth, Vishwani D. Agrawal: Estimating the Quality of Manufactured Digital Sequential Circuits. ITC 1991: 210-217

1990

j11

Sharad C. Seth, Vishwani D. Agrawal, Hassan Farhat: A Statistical Theory of Digital Circuit Testability. IEEE Trans. Computers 39(4): 582-586 (1990)

Dharam Vir Das, Sharad C. Seth, Paul T. Wagner, John C. Anderson, Vishwani D. Agrawal: An experimental study on reject ratio prediction for VLSI circuits: Kokomo revisited. ITC 1990: 712-720

Paul Kenyon, Prathima Agrawal, Sharad C. Seth: High-level microprogramming: an optimizing C compiler for a processing element of a CAD accelerator. MICRO 1990: 97-106

1989

j10

Lester Lipsky, Sharad C. Seth: Signal Probabilities in AND-OR Trees. IEEE Trans. Computers 38(11): 1558-1563 (1989)

Bhargab B. Bhattacharya, Sharad C. Seth: Design of Parity Testable Combinational Circuits. IEEE Trans. Computers 38(11): 1580-1584 (1989)

Raghu V. Hudli, Sharad C. Seth: Testability Analysis of Synchronous Sequential Circuits Based on Structural Data. ITC 1989: 364-372

1987

George Nagy, Sharad C. Seth, Kent L. Einspahr: Decoding Substitution Ciphers by Means of Word Matching with Application to OCR. IEEE Trans. Pattern Anal. Mach. Intell. 9(5): 710-715 (1987)

1985

Sharad C. Seth: Predicting Fault Coverage from Probabilistic Testability. ITC 1985: 803-807

1984

Ten-Chuan Hsiao, Sharad C. Seth: An Analysis of the Use of Rademacher-Walsh Spectrum in Compact Testing. IEEE Trans. Computers 33(10): 934-937 (1984)

Sharad C. Seth, Vishwani D. Agrawal: Characterizing the LSI Yield Equation from Wafer Test Data. IEEE Trans. on CAD of Integrated Circuits and Systems 3(2): 123-126 (1984)

1983

Sharad C. Seth, Lester Lipsky: A Simplified Method to Calculate Failure Times in Fault-Tolerant Systems. IEEE Trans. Computers 32(8): 754-760 (1983)

1981

Sharad C. Seth, K. Narayanaswamy: A Graph Model for Pattern-Sensitive Faults in Random Access Memories. IEEE Trans. Computers 30(12): 973-977 (1981)

Vishwani D. Agrawal, Sharad C. Seth, Prathima Agrawal: LSI product quality and fault coverage. DAC 1981: 196-203

1978

Kolar L. Kodandapani, Sharad C. Seth: On Combinational Networks with Restricted Fan-Out. IEEE Trans. Computers 27(4): 309-318 (1978)

1977

James M. Steckelberg, Sharad C. Seth: On a Relation Between Algebraic Programs and Turing Machines. Inf. Process. Lett. 6(6): 180-183 (1977)

Sharad C. Seth, Kolar L. Kodandapani: Diagnosis of Faults in Linear Tree Networks. IEEE Trans. Computers 26(1): 29-33 (1977)

1	Prathima Agrawal	[c8] [j15] [c4] [c1]
2	Vishwani D. Agrawal	[c15] [c12] [j15] [j13] [c6] [j11] [c5] [j6] [c1]
3	John C. Anderson	[c5]
4	Bhargab B. Bhattacharya	[c40] [j25] [c34] [j23] [c27] [c26] [c24] [c23] [j9]
5	Yi-Shing Chang	[c30]
6	Zhen Chen	[c40] [j25] [c34] [c33]
7	Kevin Cueto	[j22]
8	Hailong Cui	[j21] [c22]
9	D. Das	[j13]
10	Dharam Vir Das	[c6] [c5]
11	Kent L. Einspahr	[c20] [c19] [j19] [c16] [c13] [c12] [j17] [j8]
12	David W. Embley	[c39] [c38]
13	Hassan Farhat	[j11]
14	T. Fisher	[c14]
15	Vijay Gangaram	[c30] [c29]
16	Lee Gowen	[c7]
17	E. Guthmann	[c14]
18	Ten-Chuan Hsiao	[j7]
19	Raghu V. Hudli	[c3]
20	Ramana Chakradhar Jandhyala	[c37] [c32] [c31]
21	Hong Jiang	[c41] [c36] [c35]
22	Dongpu Jin	[c39]
23	Ashutosh Joshi	[c28] [c25]
24	K. Kalafala	[c14]
25	Jian Kang	[c30] [c29]
26	Paul Kenyon	[c4]
27	Kolar L. Kodandapani	[j3] [j1]
28	Mukkai S. Krishnamoorthy	[c39] [c38] [c37] [c32] [c31] [c25] [j14]
29	Luyang Li	[j20] [c18] [c14]
30	Yu Lin	[c25]
31	Lester Lipsky	[j10] [j5]
32	Daniel P. Lopresti	[c28] [c25]
33	Spencer Machado	[c39]
34	Shashank K. Mehta	[c25] [j21] [c22] [c20] [c19] [j19] [c17] [c16] [c13]
35	George Nagy	[c39] [c38] [c37] [j24] [c32] [c31] [c28] [c25] [j20] [c18] [c14] [j14] [j12] [j8]
36	K. Narayanaswamy	[j4]
37	Raghav K. Padmanabhan (Raghav Krishna Padmanabhan)	[c32] [c31]
38	Matt Payne	[c7]
39	N. Ranganathan (Nagarajan Ranganathan)	[j18]
40	Indranil Saha	[j23]
41	Ashok Samal	[r2] [r1] [j22] [j20] [c18] [c14] [c11] [c9] [j16]
42	Prateek Sarkar	[c14]
43	Stephen D. Scott	[c11]
44	William Silversmith	[c32] [c31]
45	S. Sivasubramaniam	[c14]
46	James M. Steckelberg	[j2]
47	Don Sylwester	[c21] [c10] [c7]
48	S. Venkatraman	[c8]
49	Mahesh Viswanathan	[j24] [j14] [j12]
50	Paul T. Wagner	[c5]
51	Mark W. Weiss	[c20] [c19]
52	Dong Xiang	[c40] [j25] [c34] [c33]
53	Yihong Xu	[j20] [c18] [c14]
54	Yuhong Yu	[c9] [j16]
55	Dongyuan Zhan	[c41] [c36] [c35]
56	Sheng Zhang	[j23] [c27] [c26] [c24] [c23]

Sharad C. Seth

Coauthor Index