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Sakir Sezer
2010 – today
- 2013
[j12]Philip O'Kane, Sakir Sezer, Kieran McLaughlin, Eul Gyu Im: SVM Training Phase Reduction Using Dataset Feature Filtering for Malware Detection. IEEE Transactions on Information Forensics and Security 8(3): 500-509 (2013)- 2012
- [j11]Kieran McLaughlin, Dwayne Burns, Ciaran Toal, Colm McKillen, Sakir Sezer: Fully hardware based WFQ architecture for high-speed QoS packet scheduling. Integration 45(1): 99-109 (2012)
- [c69]John Hurley, Antonio Munoz, Sakir Sezer: ITACA: Flexible, scalable network analysis. ICC 2012: 1069-1073
- [c68]Sakir Sezer, Dwayne Burns: Custom purpose regular expression processor architecture for network processing. ISCAS 2012: 1407-1411
- [c67]Ciaran Toal, Sakir Sezer, Dwayne Burns, Pei Xaio, Vincent F. Fusco: A 1Gbps FPGA-based wireless baseband MIMO transceiver. SoCC 2012: 202-207
- [c66]
- [c65]Ye Lu, Changlin Chen, John V. McCanny, Sakir Sezer: Design of interlock-free combined allocators for Networks-on-Chip. SoCC 2012: 358-363
- 2011
- [j10]Philip O'Kane, Sakir Sezer, Kieran McLaughlin: Obfuscation: The Hidden Malware. IEEE Security & Privacy 9(5): 41-47 (2011)
- [j9]John Hurley, Emi Garcia-Palacios, Sakir Sezer: Host-Based P2P Flow Identification and Use in Real-Time. TWEB 5(2): 7 (2011)
- [c64]Ye Lu, John V. McCanny, Sakir Sezer: Generic Low-Latency NoC Router Architecture for FPGA Computing Systems. FPL 2011: 82-89
- [c63]Antonio Munoz, Sakir Sezer, Dwayne Burns, Gareth Douglas: An Approach for Unifying Rule Based Deep Packet Inspection. ICC 2011: 1-5
- [c62]Ye Lu, John V. McCanny, Sakir Sezer: The Impact of Global Routing on the Performance of NoCs in FPGAs. ReConFig 2011: 369-374
- [c61]Yi-Pei Su, Wei-Yi Hu, Jia-Wei Lin, Yun-Chung Chen, Sakir Sezer, Sao-Jie Chen: Low power Gm-boosted differential Colpitts VCO. SoCC 2011: 247-250
- [c60]Ye Lu, John V. McCanny, Sakir Sezer: Exploring Virtual-Channel architecture in FPGA based Networks-on-Chip. SoCC 2011: 302-307
- [c59]Thianantha Arumugam, Sakir Sezer, Dwayne Burns, Vishalini Vasu: High performance multi-engine regular expression processing. SoCC 2011: 347-352
- 2010
- [j8]Liang Lu, John V. McCanny, Sakir Sezer: Reconfigurable system-on-a-chip motion estimation architecture for multi-standard video coding. IET Computers & Digital Techniques 4(5): 349-364 (2010)
- [j7]Benoît Dupasquier, Stefan Burschka, Kieran McLaughlin, Sakir Sezer: Analysis of information leakage from encrypted Skype conversations. Int. J. Inf. Sec. 9(5): 313-325 (2010)
- [j6]Andrew Marshall, Sakir Sezer, Gabriele Manganaro: Guest Editorial Special Section on 2009 IEEE System-on-Chip Conference. IEEE Trans. on Circuits and Systems 57-I(12): 3037-3038 (2010)
- [c58]Paul Miller, Weiru Liu, Chris Fowler, Huiyu Zhou, Jiali Shen, Jianbing Ma, Jianguo Zhang, WeiQi Yan, Kieran McLaughlin, Sakir Sezer: Intelligent Sensor Information System For Public Transport - To Safely Go... AVSS 2010: 533-538
- [c57]Ye Lu, Sakir Sezer, John V. McCanny: Advanced Multithreading Architecture with Hardware Based Scheduling. FPL 2010: 95-100
- [c56]Benoît Dupasquier, Stefan Burschka, Kieran McLaughlin, Sakir Sezer: On the Privacy of Encrypted Skype Communications. GLOBECOM 2010: 1-5
- [c55]Ye Lu, Sakir Sezer, John V. McCanny: TLM2.0 based timing accurate modeling method for complex NoC systems. ISCAS 2010: 2900-2903
- [c54]Sao-Jie Chen, Pao-Ann Hsiung, Chu Yu, Mao-Hsu Yen, Sakir Sezer, Michael J. Schulte, Yu Hen Hu: ARAL-CR: An adaptive reasoning and learning cognitive radio platform. ICSAMOS 2010: 324-331
- [c53]Ye Lu, Sakir Sezer, John V. McCanny: Design and analysis of an advanced static blocked multithreading architecture. SoCC 2010: 169-173
- [c52]Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns: High-Performance random data lookup for network processing. SoCC 2010: 272-277
2000 – 2009
- 2009
- [j5]Liang Lu, John V. McCanny, Sakir Sezer: Subpixel Interpolation Architecture for Multistandard Video Motion Estimation. IEEE Trans. Circuits Syst. Video Techn. 19(12): 1897-1901 (2009)
- [j4]Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Xin Yang: Design and Implementation of a Field Programmable CRC Circuit Architecture. IEEE Trans. VLSI Syst. 17(8): 1142-1147 (2009)
- [c51]John Hurley, Emi Garcia-Palacios, Sakir Sezer: Classification of P2P and HTTP Using Specific Protocol Characteristics. EUNICE 2009: 31-40
- [c50]Yongping Liu, Sakir Sezer, John V. McCanny: NFA decomposition and multiprocessing architecture for parallel regular expression processing. SoCC 2009: 347-350
- [c49]Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns: DDR3 based lookup circuit for high-performance network processing. SoCC 2009: 351-354
- 2008
- [j3]Motasem A. Aldiab, Emi Garcia-Palacios, Danny Crookes, Sakir Sezer: Packet Classification by Multilevel Cutting of the Classification Space: An Algorithmic-Architectural Solution for IP Packet Classification in Next Generation Networks. Journal Comp. Netw. and Communic. 2008 (2008)
- [j2]Kieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias G. Noll: A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. IEEE Trans. VLSI Syst. 16(7): 781-791 (2008)
- [c48]Khalid Latif, Moazzam Fareed Niazi, Hannu Tenhunen, Tiberiu Seceleanu, Sakir Sezer: Application development flow for on-chip distributed architectures. SoCC 2008: 163-168
- [c47]Liang Lu, John V. McCanny, Sakir Sezer: Multi-standard sub-pixel interpolation architecture for video Motion Estimation. SoCC 2008: 229-232
- [c46]Xin Yang, Jun Mu, Sakir Sezer, John V. McCanny, Earl E. Swartzlander Jr.: High performance IP lookup circuit using DDR SDRAM. SoCC 2008: 371-374
- 2007
- [c45]Liang Lu, John V. McCanny, Sakir Sezer: Systolic Array Based Architecture for Variable Block-Size Motion Estimation. AHS 2007: 160-168
- [c44]Ciaran Toal, Dwayne Burns, Kieran McLaughlin, Sakir Sezer, Stephen O'Kane: An RLDRAM II Implementation of a 10Gbps Shared Packet Buffer for Network Processing. AHS 2007: 613-618
- [c43]Motasem Abdelghani, Sakir Sezer, Emi Garcia, Jun Mu, Ciaran Toal: FPGA-Based Lookup Circuit for Session-Based IP Packet Classification. AHS 2007: 619-624
- [c42]Kieran McLaughlin, Sakir Sezer: High-Speed IP Address Lookups Using Hardware Based Tree Structures. AHS 2007: 625-632
- [c41]Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns: Novel Content Addressable Memory Architecture for Adaptive Systems. AHS 2007: 633-640
- [c40]Liang Lu, John V. McCanny, Sakir Sezer: Reconfigurable Motion Estimation Architecture for Multi-standard Video Compression. ASAP 2007: 253-259
- [c39]Dwayne Burns, Ciaran Toal, Kieran McLaughlin, Sakir Sezer, Mike Hutton, Kevin Cackovic: An FPGA Based Memory Efficient Shared Buffer Implementation. FPL 2007: 661-664
- [c38]Liang Lu, John V. McCanny, Sakir Sezer: Reconfigurable video motion estimation processor. SoCC 2007: 55-58
- [c37]Jun Mu, Sakir Sezer, Gareth Douglas, Dwayne Burns, Emi Garcia, Mike Hutton, Kevin Cackovic: Accelerating pattern matching for DPI. SoCC 2007: 83-86
- [c36]Ciaran Toal, Sakir Sezer, Xin Yang, Kieran McLaughlin, Dwayne Burns, Tiberiu Seceleanu: Programmable CRC circuit architecture. SoCC 2007: 123-126
- [c35]Xin Yang, Sakir Sezer, John V. McCanny, Dwayne Burns: A versatile content addressable memory architecture. SoCC 2007: 215-218
- 2006
- [c34]Stephen O'Kane, Sakir Sezer, Lum Soong Lit: A Study of Shared Buffer Memory Segmentation for Packet Switched Networks. AICT/ICIW 2006: 55
- [c33]Friederich Kupzog, Holger Blume, Tobias G. Noll, Kieran McLaughlin, Sakir Sezer, John V. McCanny: Design and Analysis of Matching Circuit Architectures for a Closest Match Lookup. AICT/ICIW 2006: 56
- [c32]Kieran McLaughlin, Niall O'Connor, Sakir Sezer: Exploring CAM Design For Network Processing Using FPGA Technology. AICT/ICIW 2006: 84
- [c31]Kieran McLaughlin, Friederich Kupzog, Holger Blume, Sakir Sezer, Tobias G. Noll, John V. McCanny: Design and analysis of matching circuit architectures for a closest match lookup. IPDPS 2006
- [c30]Ciaran Toal, Sakir Sezer: Investigation into programmability for layer 2 protocol frame delineation architectures. IPDPS 2006
- [c29]Colm McKillen, Sakir Sezer, Xin Yang: High performance service-time-stamp computation for WFQ IP packet scheduling. ISVLSI 2006: 65-70
- [c28]
- [c27]Kieran McLaughlin, Sakir Sezer, Holger Blume, Xin Yang, Friederich Kupzog, Tobias G. Noll: A Scalable Packet Sorting Circuit for High-Speed WFQ Packet Scheduling. SoCC 2006: 271-274
- 2005
- [c26]Motasem Abdelghani, Sakir Sezer, Emi Garcia, Jun Mu: Packet Classification Using Adaptive Rules Cutting (ARC). AICT/SAPIR/ELETE 2005: 28-33
- [c25]Kieran McLaughlin, Stephen O'Kane, Sakir Sezer: Implementing High Speed IP Address Lookups in Hardware. AICT/SAPIR/ELETE 2005: 140-144
- [c24]Steven Walsh, Emi Garcia, Sakir Sezer: Assessing the Impact of Rainfall on System Bandwidth for Broadband Fixed Wireless Applications. AICT/SAPIR/ELETE 2005: 279-283
- [c23]P. Moore, Máire McLoone, Sakir Sezer: Reconfigurable Instruction Interface Architecture for Private-Key Cryptography on the Altera Nios-II Processor. AICT/SAPIR/ELETE 2005: 296-299
- [c22]Stephen O'Kane, Colm McKillen, Sakir Sezer: The Design and Implementation of a Shared Packet Buffer Architecture for Fixed and Variable Sized Packets. AICT/SAPIR/ELETE 2005: 352-356
- [c21]Ciaran Toal, Sakir Sezer: A 10 Gbps GFP Frame Delineation Circuit with Single Bit Error Correction on an FPGA. AICT/SAPIR/ELETE 2005: 357-362
- [c20]Stephen O'Kane, Sakir Sezer, Ciaran Toal: Design and implementation of a shared buffer architecture for a gigabit Ethernet packet switch. SoCC 2005: 283-286
- 2004
- [c19]Stephen O'Kane, Sakir Sezer: An investigation into the design of high-performance shared buffer architectures based on FPGA technology with embedded memory. FPT 2004: 461-464
- [c18]Sakir Sezer, Emi Garcia-Palacios, Ciaran Toal, Stephen Dawson: Architecture and implementation of a novel tag computation circuit for broadband wireless access packet scheduling. ICC 2004: 3979-3983
- [c17]V. Stewart, C. F. N. Cowan, Sakir Sezer: Adaptive Echo Cancellation for Packet-Based Networks. ICT 2004: 516-525
- [c16]Emi Garcia-Palacios, Sakir Sezer, Ciaran Toal, Stephen Dawson: Implementation of a Novel Credit Based SCFQ Scheduler for Broadband Wireless Access. ICT 2004: 876-884
- [c15]Ciaran Toal, Sakir Sezer: The Implementation of Scalable ATM Frame Delineation Circuits. ICT 2004: 1047-1056
- [c14]Stephen Dawson, Sakir Sezer: Web Based Service Provision - A Case Study: Electronic Design Automation. ICT 2004: 1057-1066
- [c13]Sakir Sezer, Ciaran Toal, Emi Garcia, V. Stewart: A Reconfigurable Tag Computation Architecture for Terabit Packet Scheduling. IPDPS 2004
- [c12]Ciaran Toal, Sakir Sezer: Exploration of GFP frame delineation architectures for network processing. SoCC 2004: 159-162
- [c11]Colm McKillen, Sakir Sezer: A weighted fair queuing finishing tag computation architecture and implementation. SoCC 2004: 270-273
- 2003
- [c10]Ciaran Toal, Sakir Sezer, Xing Yu: A Pipelined SoPC Architecture for 2.5 Gbps Network Processing. FCCM 2003: 271-272
- [c9]Brendan McAllister, Sakir Sezer, Ciaran Toal: Custom Tag Computation Circuit for a 10Gbps SCFQ Scheduler. FPL 2003: 1149-1152
- [c8]Stephen Dawson, Sakir Sezer: A Framework for Remote EDA Tooling and Distributed Resource Management. International Conference on Internet Computing 2003: 213-218
- [c7]Ciaran Toal, Sakir Sezer: A Programmable and Highly Pipelined PPP Architecture for Gigabit IP over SDH/SONET. IPDPS 2003: 179
- [c6]
- 2001
- [j1]Jean-Paul Heron, Roger Woods, Sakir Sezer, Richard H. Turner: Development of a Run-Time Reconfiguration System with Low Reconfiguration Overhead. VLSI Signal Processing 28(1-2): 97-113 (2001)
- [c5]Sakir Sezer, Eimear Stewart, Marc Carson, Claire Greenwood: System on a FPGA Virtual Concatenation. FCCM 2001: 257-258
- 2000
- [c4]Alan Marshall, Emi Garcia-Palacios, Sakir Sezer, David Chieng: Performance Analysis of Access Points In Cellular Wireless ATM Networks. MMNS 2000: 31-44
1990 – 1999
- 1999
- [c3]Richard H. Turner, Roger Woods, Sakir Sezer, Jean-Paul Heron: A Virtual Hardware Handler for RTR Systems. FCCM 1999: 262-263
- [c2]Alan Marshall, Sakir Sezer: The Influence of Cumulative Switch Delay in Multiple Service Class Networks. IMSA 1999: 409-414
- 1998
- [c1]Sakir Sezer, Roger Woods, Jean-Paul Heron, Alan J. Marshall: Fast Partial Reconfiguration for FCCMs. FCCM 1998: 318-319
Coauthor Index
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last updated on 2013-03-15 18:02 CET by the dblp team