Naresh R. Shanbhag

Rami A. Abdallah, Naresh R. Shanbhag: Robust and Energy Efficient Multimedia Systems via Likelihood Processing. IEEE Transactions on Multimedia 15(2): 257-267 (2013)

Eric P. Kim, Naresh R. Shanbhag: Soft N-Modular Redundancy. IEEE Trans. Computers 61(3): 323-336 (2012)

Rajan Narasimha, Minwei Lu, Naresh R. Shanbhag, Andrew C. Singer: BER-Optimal Analog-to-Digital Converters for Communication Links. IEEE Transactions on Signal Processing 60(7): 3683-3691 (2012)

Rami A. Abdallah, Naresh R. Shanbhag: A 14.5 fJ/cycle/k-gate, 0.33 V ECG processor in 45nm CMOS using statistical error compensation. CICC 2012: 1-4

Adam C. Faust, Rajan Narasimha, Karan S. Bhatia, Ankit Srivastava, Chhay Kong, Hyeon-Min Bae, Elyse Rosenbaum, Naresh R. Shanbhag: FEC-based 4 Gb/s backplane transceiver in 90nm CMOS. CICC 2012: 1-4

Rajan Narasimha, Georg Zeitler, Naresh R. Shanbhag, Andrew C. Singer, Gerhard Kramer: System-driven metrics for the design and adaptation of analog to digital converters. ICASSP 2012: 5281-5284

Karthik V. Aadithya, Yingyan Lin, Chenjie Gu, Aolin Xu, Jaijeet S. Roychowdhury, Naresh R. Shanbhag: A fully automated technique for constructing FSM abstractions of non-ideal latches in communication systems. ICASSP 2012: 5289-5292

Eric P. Kim, Naresh R. Shanbhag: Energy-Efficient LDPC Decoders Based on Error-Resiliency. SiPS 2012: 149-154

Naresh R. Shanbhag, Massimo Poncino, Pai H. Chou, Ajith Amerasekera (Eds.): International Symposium on Low Power Electronics and Design, ISLPED'12, Redondo Beach, CA, USA - July 30 - August 01, 2012. ACM 2012, isbn 978-1-4503-1249-3

Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag: VLSI Architectures for Soft-Decision Decoding of Reed-Solomon Codes. IEEE Transactions on Information Theory 57(2): 648-667 (2011)

Eric P. Kim, Daniel J. Baker, Sriram Narayanan, Douglas L. Jones, Naresh R. Shanbhag: Low power and error resilient PN code acquisition filter via statistical error compensation. CICC 2011: 1-4

Rami A. Abdallah, Yu-Hung Lee, Naresh R. Shanbhag: Timing error statistics for energy-efficient robust DSP systems. DATE 2011: 285-288

Naresh R. Shanbhag, Andrew C. Singer: System-assisted analog mixed-signal design. DATE 2011: 1491-1496

Aditya Gupta, Andrew C. Singer, Naresh R. Shanbhag: Least squares approximation and polyphase decomposition for pipelining recursive filters. ICASSP 2011: 1661-1664

Rami A. Abdallah, Pradeep S. Shenoy, Naresh R. Shanbhag, Philip T. Krein: System energy minimization via joint optimization of the DC-DC converter and the core. ISLPED 2011: 97-102

Eric P. Kim, Naresh R. Shanbhag: An energy-efficient multiple-input multiple-output (MIMO) detector architecture. SiPS 2011: 239-244

Rami A. Abdallah, Naresh R. Shanbhag: Minimum-Energy Operation Via Error Resiliency. Embedded Systems Letters 2(4): 115-118 (2010)

Rajan Narasimha, Naresh R. Shanbhag: Design of Energy-Efficient High-Speed Links via Forward Error Correction. IEEE Trans. on Circuits and Systems 57-II(5): 359-363 (2010)

Sriram Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag: Computation as estimation: a general framework for robustness and energy efficiency in SoCs. IEEE Transactions on Signal Processing 58(8): 4416-4421 (2010)

Girish Varatkar, Shrikanth S. Narayanan, Naresh R. Shanbhag, Douglas L. Jones: Stochastic Networked Computation. IEEE Trans. VLSI Syst. 18(10): 1421-1432 (2010)

Naresh R. Shanbhag, Rami A. Abdallah, Rakesh Kumar, Douglas L. Jones: Stochastic computation. DAC 2010: 859-864

Eric P. Kim, Naresh R. Shanbhag: Soft NMR: Analysis & application to DSP systems. ICASSP 2010: 1494-1497

Rami A. Abdallah, Naresh R. Shanbhag: Robust and energy-efficient DSP systems via output probability processing. ICCD 2010: 38-44

Minwei Lu, Naresh R. Shanbhag, Andrew C. Singer: BER-optimal analog-to-digital converters for communication links. ISCAS 2010: 1029-1032

Yuriy M. Greshishchev, Franz Dielacher, Michael Flynn, Donhee Ham, Naresh R. Shanbhag, Takuji Yamamoto: Transceiver circuits for optical communications. ISSCC 2010: 514-515

Naresh R. Shanbhag, Koichi Yamaguchi, Robert Payne: Energy-efficient high-speed interfaces. ISSCC 2010: 524-525

Vojin G. Oklobdzija, Barry Pangle, Naehyuck Chang, Naresh R. Shanbhag, Chris H. Kim (Eds.): Proceedings of the 2010 International Symposium on Low Power Electronics and Design, 2010, Austin, Texas, USA, August 18-20, 2010. ACM 2010, isbn 978-1-4503-0146-6

Rami A. Abdallah, Naresh R. Shanbhag: Error-resilient low-power Viterbi decoder architectures. IEEE Transactions on Signal Processing 57(12): 4906-4917 (2009)

Rajan Narasimha, Nirmal Warke, Naresh R. Shanbhag: Impact of DFE Error Propagation on FEC-Based High-Speed I/O Links. GLOBECOM 2009: 1-6

Junho Cho, Naresh R. Shanbhag, Wonyong Sung: Low-power implementation of a high-throughput LDPC decoder for IEEE 802.11N standard. SiPS 2009: 040-045

Rami A. Abdallah, Seok-Jun Lee, Manish Goel, Naresh R. Shanbhag: Low-power pre-decoding based viterbi decoder for tail-biting convolutional codes. SiPS 2009: 185-190

Naresh R. Shanbhag, Subhasish Mitra, Gustavo de Veciana, Michael Orshansky, Radu Marculescu, Jaijeet S. Roychowdhury, Douglas L. Jones, Jan M. Rabaey: The Search for Alternative Computational Paradigms. IEEE Design & Test of Computers 25(4): 334-343 (2008)

Srinivasa R. Sridhara, Ganesh Balamurugan, Naresh R. Shanbhag: Joint Equalization and Coding for On-Chip Bus Communication. IEEE Trans. VLSI Syst. 16(3): 314-318 (2008)

Girish Varatkar, Naresh R. Shanbhag: Error-Resilient Motion Estimation Architecture. IEEE Trans. VLSI Syst. 16(10): 1399-1412 (2008)

Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones: Trends in energy-efficiency and robustness using stochastic sensor network-on-a-chip. ACM Great Lakes Symposium on VLSI 2008: 351-354

Shrikanth Narayanan, Girish Varatkar, Douglas L. Jones, Naresh R. Shanbhag: Computation as estimation: Estimation-theoretic IC design improves robustness and reduces power consumption. ICASSP 2008: 1421-1424

Girish Varatkar, Sriram Narayanan, Naresh R. Shanbhag, Douglas L. Jones: Variation-tolerant, low-power PN-code acquisition using stochastic sensor NOC. ISCAS 2008: 380-383

Rami A. Abdallah, Naresh R. Shanbhag: Error-resilient low-power Viterbi decoders. ISLPED 2008: 111-116

Rami A. Abdallah, Naresh R. Shanbhag: Error-resilient low-power Viterbi decoders via state clustering. SiPS 2008: 221-226

Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for Reliable On-Chip Buses: A Class of Fundamental Bounds and Practical Codes. IEEE Trans. on CAD of Integrated Circuits and Systems 26(5): 977-982 (2007)

Girish Varatkar, Naresh R. Shanbhag: Variation-Tolerant Motion Estimation Architecture. SiPS 2007: 126-131

Ming Zhang, Naresh R. Shanbhag: Soft-Error-Rate-Analysis (SERA) Methodology. IEEE Trans. on CAD of Integrated Circuits and Systems 25(10): 2140-2155 (2006)

Byonghyo Shim, Naresh R. Shanbhag: Energy-efficient soft error-tolerant digital signal processing. IEEE Trans. VLSI Syst. 14(4): 336-348 (2006)

Ming Zhang, Subhasish Mitra, T. M. Mak, Norbert Seifert, Nicholas J. Wang, Quan Shi, Kee Sup Kim, Naresh R. Shanbhag, Sanjay J. Patel: Sequential Element Design With Built-In Soft Error Resilience. IEEE Trans. VLSI Syst. 14(12): 1368-1378 (2006)

Girish Varatkar, Naresh R. Shanbhag: Energy-efficient motion estimation using error-tolerance. ISLPED 2006: 113-118

Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag: Linear turbo equalization analysis via BER transfer and EXIT charts. IEEE Transactions on Signal Processing 53(8-1): 2883-2897 (2005)

Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for system-on-chip networks: a unified framework. IEEE Trans. VLSI Syst. 13(6): 655-667 (2005)

Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: Area-efficient high-throughput MAP decoder architectures. IEEE Trans. VLSI Syst. 13(8): 921-933 (2005)

Naresh R. Shanbhag, Keshab K. Parhi: Guest Editorial. VLSI Signal Processing 39(1-2): 5-6 (2005)

Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: Energy Efficient VLSI Architecture for Linear Turbo Equalizer. VLSI Signal Processing 39(1-2): 49-62 (2005)

Mohammad M. Mansour, Naresh R. Shanbhag: A Novel Design Methodology for High-Performance Programmable Decoder Cores for AA-LDPC Codes. VLSI Signal Processing 40(3): 371-382 (2005)

Ming Zhang, Naresh R. Shanbhag: An energy-efficient circuit technique for single event transient noise-tolerance. ISCAS (1) 2005: 636-639

Srinivasa R. Sridhara, Naresh R. Shanbhag: A low-power bus design using joint repeater insertion and coding. ISLPED 2005: 99-102

Srinivasa R. Sridhara, Naresh R. Shanbhag, Ganesh Balamurugan: Joint Equalization and Coding for On-Chip Bus Communication. ISQED 2005: 642-647

Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for Reliable On-Chip Buses: Fundamental Limits and Practical Codes. VLSI Design 2005: 417-422

Naresh R. Shanbhag: Reliable and Efficient System-on-Chip Design. IEEE Computer 37(3): 42-50 (2004)

Byonghyo Shim, Srinivasa R. Sridhara, Naresh R. Shanbhag: Reliable low-power digital signal processing via reduced precision redundancy. IEEE Trans. VLSI Syst. 12(5): 497-510 (2004)

Naresh R. Shanbhag: A communication-theoretic design paradigm for reliable SOCs. DAC 2004: 76

Srinivasa R. Sridhara, Naresh R. Shanbhag: Coding for system-on-chip networks: a unified framework. DAC 2004: 103-106

Arshad Ahmed, Ralf Koetter, Naresh R. Shanbhag: VLSI architectures for soft-decision decoding of Reed-Solomon codes. ICC 2004: 2584-2590

Ming Zhang, Naresh R. Shanbhag: A soft error rate analysis (SERA) methodology. ICCAD 2004: 111-118

Srinivasa R. Sridhara, Arshad Ahmed, Naresh R. Shanbhag: Area and Energy-Efficient Crosstalk Avoidance Codes for On-Chip Buses. ICCD 2004: 12-17

Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: Switching methods for linear turbo equalization. ISCAS (3) 2004: 601-604

Byonghyo Shim, Naresh R. Shanbhag: Complexity analysis of multicarrier and single-carrier systems for very high-speed digital subscriber line. IEEE Transactions on Signal Processing 51(1): 282-292 (2003)

Lei Wang, Naresh R. Shanbhag: Low-power filtering via adaptive error-cancellation. IEEE Transactions on Signal Processing 51(2): 575-583 (2003)

Lei Wang, Naresh R. Shanbhag: Energy-efficiency bounds for deep submicron VLSI systems in the presence of noise. IEEE Trans. VLSI Syst. 11(2): 254-269 (2003)

Lei Wang, Naresh R. Shanbhag: Low-power MIMO signal processing. IEEE Trans. VLSI Syst. 11(3): 434-445 (2003)

Mohammad M. Mansour, Naresh R. Shanbhag: VLSI architectures for SISO-APP decoders. IEEE Trans. VLSI Syst. 11(4): 627-650 (2003)

Mohammad M. Mansour, Naresh R. Shanbhag: High-throughput LDPC decoders. IEEE Trans. VLSI Syst. 11(6): 976-996 (2003)

Seok-Jun Lee, Andrew C. Singer, Naresh R. Shanbhag: Analysis of linear turbo equalizer via EXIT chart. GLOBECOM 2003: 2237-2242

Ganesh Balamurugan, Naresh R. Shanbhag: Modeling and Mitigation of Jitter in Multi-Gbps Source-Synchronous I/O Links. ICCD 2003: 254-260

Mohammad M. Mansour, Naresh R. Shanbhag: Architecture-aware low-density parity-check codes. ISCAS (2) 2003: 57-60

Byonghyo Shim, Naresh R. Shanbhag: Performance analysis of algorithmic noise-tolerance techniques. ISCAS (4) 2003: 113-116

Hyeon-Min Bae, Naresh R. Shanbhag: High bandwidth transimpedance amplifier design using active transmission lines. ISCAS (1) 2003: 253-256

Seok-Jun Lee, Naresh R. Shanbhag, Andrew C. Singer: A low-power VLSI architecture for turbo decoding. ISLPED 2003: 366-371

Naresh R. Shanbhag: Reliable and energy-efficient digital signal processing. DAC 2002: 830-835

Mohammad M. Mansour, Naresh R. Shanbhag: Turbo decoder architectures for low-density parity-check codes. GLOBECOM 2002: 1383-1388

Mohammad M. Mansour, Naresh R. Shanbhag: Design methodology for high-speed iterative decoder architectures. ICASSP 2002: 3085-3088

Mohammad M. Mansour, Naresh R. Shanbhag: Simplified current and delay models for deep submicron CMOS digital circuits. ISCAS (5) 2002: 109-112

Mohammad M. Mansour, Naresh R. Shanbhag: Low-power VLSI decoder architectures for LDPC codes. ISLPED 2002: 284-289

Dilip V. Sarwate, Naresh R. Shanbhag: High-speed architectures for Reed-Solomon decoders. IEEE Trans. VLSI Syst. 9(5): 641-655 (2001)

Rajamohana Hegde, Naresh R. Shanbhag: Soft digital signal processing. IEEE Trans. VLSI Syst. 9(6): 813-823 (2001)

Swaroop Appadwedula, Manish Goel, Naresh R. Shanbhag, Douglas L. Jones, Kannan Ramchandran: Total System Energy Minimization for Wireless Image Transmission. VLSI Signal Processing 27(1-2): 99-117 (2001)

Wayne Burleson, Naresh R. Shanbhag: Guest Editorial: Reconfigurable Signal Processing Systems. VLSI Signal Processing 28(1-2): 5-6 (2001)

Lei Wang, Naresh R. Shanbhag: Low-power AEC-based MIMO signal processing for gigabit ethernet 1000Base-T transceivers. ISLPED 2001: 334-339

Rajamohana Hegde, Naresh R. Shanbhag: Toward achieving energy efficiency in presence of deep submicron noise. IEEE Trans. VLSI Syst. 8(4): 379-391 (2000)

Ki-Wook Kim, Kwang-Hyun Baek, Naresh R. Shanbhag, C. L. Liu, Sung-Mo Kang: Coupling-Driven Signal Encoding Scheme for Low-Power Interface Design. ICCAD 2000: 318-321

Naresh R. Shanbhag, K. Soumyanath, Samuel Martin: Reliable low-power design in the presence of deep submicron noise (embedded tutorial session). ISLPED 2000: 295-302

Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: A coding framework for low-power address and data busses. IEEE Trans. VLSI Syst. 7(2): 212-221 (1999)

Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Information-theoretic bounds on average signal transition activity [VLSI systems]. IEEE Trans. VLSI Syst. 7(3): 359-368 (1999)

Manish Goel, Naresh R. Shanbhag: Dynamic algorithm transformations (DAT)-a systematic approach to low-power reconfigurable signal processing. IEEE Trans. VLSI Syst. 7(4): 463-476 (1999)

Rajamohana Hegde, Naresh R. Shanbhag: Lower bounds on energy dissipation and noise-tolerance for deep submicron VLSI. ISCAS (6) 1999: 334-337

Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Low-power distributed arithmetic architectures using nonuniform memory partitioning. ISCAS (3) 1999: 470-473

Lei Wang, Naresh R. Shanbhag: Noise-tolerant dynamic circuit design. ISCAS (1) 1999: 549-552

Ganesh Balamurugan, Naresh R. Shanbhag: Energy-efficient dynamic circuit design in the presence of crosstalk noise. ISLPED 1999: 24-29

Rajamohana Hegde, Naresh R. Shanbhag: Energy-efficient signal processing via algorithmic noise-tolerance. ISLPED 1999: 30-35

Sudhakar Bobba, Ibrahim N. Hajj, Naresh R. Shanbhag: Analytical Expressions for Power Dissipation of Macro-blocks in DSP Architectures. VLSI Design 1999: 358-

Naresh R. Shanbhag: Algorithms Transformation Techniques for Low-Power Wireless VLSI Systems Design. IJWIN 5(2): 147-171 (1998)

Naresh R. Shanbhag, Gi-Hong Im: VLSI systems design of 51.84 Mb/s transceivers for ATM-LAN and broadband access. IEEE Transactions on Signal Processing 46(5): 1403-1416 (1998)

Manish Goel, Naresh R. Shanbhag: Finite-precision analysis of the pipelined strength-reduced adaptive filter. IEEE Transactions on Signal Processing 46(6): 1763-1769 (1998)

Gi-Hong Im, Naresh R. Shanbhag: A pipelined adaptive NEXT canceller. IEEE Transactions on Signal Processing 46(8): 2252-2258 (1998)

Rajamohana Hegde, Naresh R. Shanbhag: Energy-efficiency in presence of deep submicron noise. ICCAD 1998: 228-234

Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Decorrelating (DECOR) transformations for low-power adaptive filters. ISLPED 1998: 250-255

Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Coding for Low-Power Address and Data Busses: A Source-Coding Framework and Applications. VLSI Design 1998: 18-23

Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Analytical estimation of signal transition activity from word-level statistics. IEEE Trans. on CAD of Integrated Circuits and Systems 16(7): 718-733 (1997)

Naresh R. Shanbhag, Manish Goel: Low-power adaptive filter architectures and their application to 51.84 Mb/s ATM-LAN. IEEE Transactions on Signal Processing 45(5): 1276-1290 (1997)

Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Analytical Estimation of Transition Activity From Word-Level Signal Statistics. DAC 1997: 582-587

Sumant Ramprasad, Naresh R. Shanbhag, Ibrahim N. Hajj: Achievable bounds on signal transition activity. ICCAD 1997: 126-129

Manish Goel, Naresh R. Shanbhag: Dynamic algorithm transformation (DAT) for low-power adaptive signal processing. ISLPED 1997: 161-166

Naresh R. Shanbhag, Gi-Hong Im: Pipelined adaptive IIR filter architectures using scattered and relaxed look-ahead transformations. IEEE Transactions on Signal Processing 44(7): 1841-1847 (1996)

Naresh R. Shanbhag: Lower bounds on power dissipation for DSP algorithms. ISLPED 1996: 43-48

Manish Goel, Naresh R. Shanbhag: Low-power adaptive filter architectures via strength reduction. ISLPED 1996: 217-220

Naresh R. Shanbhag, Keshab K. Parhi: Pipelined adaptive DFE architectures using relaxed look-ahead. IEEE Transactions on Signal Processing 43(6): 1368-1385 (1995)

Naresh R. Shanbhag, Gi-Hong Im: Pipelined Adaptive IIR Filter Architecture. ISCAS 1995: 558-561

Naresh R. Shanbhag, Keshab K. Parhi: A pipelined adaptive lattice filter architecture. IEEE Transactions on Signal Processing 41(5): 1925-1939 (1993)

Naresh R. Shanbhag, Keshab K. Parhi: Roundoff error analysis of the pipelined ADPCM coder. ISCAS 1993: 886-889

Naresh R. Shanbhag, Keshab K. Parhi: A Pipelined Adaptive Differential Vector Quantizer for Low-power Speech Coding Applications. ISCAS 1993: 1956-1958

Naresh R. Shanbhag: An improved systolic architecture for 2-D digital filters. IEEE Transactions on Signal Processing 39(5): 1195-1202 (1991)