- CSB - MetaPress - Google - Bing - Yahoo
 | 2008 | |
|---|---|---|
| c30 |      | Sambuddha Bhattacharya, Shabbir H. Batterywala, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: On Efficient and Robust Constraint Generation for Practical Layout Legalization. ISQED 2008: 379-384 |
| c29 | | Shabbir H. Batterywala, Sambuddha Bhattacharya, Subramanian Rajagopalan, Hi-Keung Tony Ma, Narendra V. Shenoy: Cell Swapping Based Migration Methodology for Analog and Custom Layouts. ISQED 2008: 450-455 |
| 2007 | ||
| j5 | | Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Gaussian Random Variables. IEEE Trans. on CAD of Integrated Circuits and Systems 26(8): 1522-1533 (2007) |
| c28 | | Debjit Sinha, Jianfeng Luo, Subramanian Rajagopalan, Shabbir H. Batterywala, Narendra V. Shenoy, Hai Zhou: Impact of Modern Process Technologies on the Electrical Parameters of Interconnects. VLSI Design 2007: 875-880 |
| 2006 | ||
| j4 | | Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical Timing Yield Optimization by Gate Sizing. IEEE Trans. VLSI Syst. 14(10): 1140-1146 (2006) |
| c27 | | Debjit Sinha, Hai Zhou, Narendra V. Shenoy: Advances in Computation of the Maximum of a Set of Random Variables. ISQED 2006: 306-311 |
| 2005 | ||
| c26 |  | Debjit Sinha, Narendra V. Shenoy, Hai Zhou: Statistical gate sizing for timing yield optimization. ICCAD 2005: 1037-1041 |
| 2004 | ||
| c25 | | Narendra V. Shenoy, Jamil Kawa, Raul Camposano: Design automation for mask programmable fabrics. DAC 2004: 192-197 |
| c24 | | Shabbir H. Batterywala, Narendra V. Shenoy: Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. VLSI Design 2004: 989-994 |
| 2003 | ||
| c23 | | Chi-Foon Chan, Deirdre Hanford, Jian Yue Pan, Narendra V. Shenoy, Mahesh Mehendale, A. Vasudevan, Shaojun Wei: Emerging markets: design goes global. DAC 2003: 195 |
| c22 | | Shabbir H. Batterywala, Narendra V. Shenoy: A Method to Estimate Slew and Delay in Coupled Digital Circuits. VLSI Design 2003: 411-416 |
| 2002 | ||
| j3 | | Hai Zhou, Narendra V. Shenoy, William Nicholls: Efficient minimum spanning tree construction without Delaunay triangulation. Inf. Process. Lett. 81(5): 271-276 (2002) |
| c21 | | |
| c20 | | Shabbir H. Batterywala, Narendra V. Shenoy, William Nicholls, Hai Zhou: Track assignment: a desirable intermediate step between global routing and detailed routing. ICCAD 2002: 59-66 |
| c19 | | Stan Y. Liao, Narendra V. Shenoy, William Nicholls: An Efficient External-Memory Implementation of Region Query with Application to Area Routing. ICCD 2002: 36-41 |
| 2001 | ||
| c18 | | Hai Zhou, Narendra V. Shenoy, William Nicholls: Efficient minimum spanning tree construction without Delaunay triangulation. ASP-DAC 2001: 192-197 |
| c17 | | Hai Zhou, Narendra V. Shenoy, William Nicholls: Timing Analysis with Crosstalk as Fixpoints on Complete Lattice. DAC 2001: 714-719 |
| 1999 | ||
| c16 | | Narendra V. Shenoy, Mahesh A. Iyer, Robert F. Damiano, Kevin Harer, Hi-Keung Tony Ma, Paul Thilking: A Robust Solution to the Timing Convergence Problem in High-Performance Design. ICCD 1999: 250-257 |
| 1997 | ||
| j2 | | |
| c15 | | Ramsey W. Haddad, Lukas P. P. P. van Ginneken, Narendra V. Shenoy: Discrete Drive Selection for Continuous Sizing. ICCD 1997: 110-115 |
| c14 | | Kurt Keutzer, A. Richard Newton, Narendra V. Shenoy: The future of logic synthesis and physical design in deep-submicron process geometries. ISPD 1997: 218-224 |
| 1996 | ||
| c13 | | Ralph H. J. M. Otten, Lukas P. P. P. van Ginneken, Narendra V. Shenoy: Embedded tutorial: Speed - new paradigms in design for performance. ICCAD 1996: 700 |
| 1995 | ||
| c12 | | Alexander Saldanha, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Functional clock schedule optimization. VLSI Design 1995: 93-98 |
| 1994 | ||
| j1 | | Luciano Lavagno, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli: Linear programming for hazard elimination in asynchronous circuits. VLSI Signal Processing 7(1-2): 137-160 (1994) |
| c11 | | |
| 1993 | ||
| c10 | | Masamichi Kawarabayashi, Narendra V. Shenoy, Alberto L. Sangiovanni-Vincentelli: A Verification Technique for Gated Clock. DAC 1993: 123-127 |
| c9 | | Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Resynthesis of Multi-Phase Pipelines. DAC 1993: 490-496 |
| c8 | | Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Minimum padding to satisfy short path constraints. ICCAD 1993: 156-161 |
| 1992 | ||
| c7 | | Narendra V. Shenoy, Kanwar Jit Singh, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: On the Temporal Equivalence of Sequential Circuits. DAC 1992: 405-409 |
| c6 | | |
| c5 | | Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Graph algorithms for clock schedule optimization. ICCAD 1992: 132-136 |
| 1991 | ||
| c4 | | Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Improved Logic Synthesis Algorithms for Table Look Up Architectures. ICCAD 1991: 564-567 |
| c3 | | Rajeev Murgai, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Performance Directed Synthesis for Table Look Up Programmable Gate Arrays. ICCAD 1991: 572-575 |
| c2 | | Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Retiming of Circuits with Single Phase Transparent Latches. ICCD 1991: 86-89 |
| 1990 | ||
| c1 | | Rajeev Murgai, Yoshihito Nishizaki, Narendra V. Shenoy, Robert K. Brayton, Alberto L. Sangiovanni-Vincentelli: Logic Synthesis for Programmable Gate Arrays. DAC 1990: 620-625 |
Colors in the list of coauthors
Last update Sat May 18 20:25:48 2013 CET by the DBLP Team —
Data released under the ODC-BY 1.0 license — See also our legal information page